Inventor
Katsunao Kanari
Inventor
Kawasaki, JP
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique33%
G11CStatic stores22%
H10DInorganic electric semiconductor devices22%
G06FElectric digital data processing11%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
PatentTitleYear
9,018,981'Latch circuit and clock control circuit'20158,185,855'Capacitor-cell, integrated circuit, and designing and manufacturing methods'20128,151,152'Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method'20127,961,547'Memory device using a common write word line and a common read bit line'20117,817,492'Memory device using SRAM circuit'20107,449,731'Semiconductor gate circuit and delay circuit comprising series connected CMOS transistors'20087,310,011'Clock signal adjuster circuit'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2015Patents assigned to FUJITSU LTD (7)· patent assignee history
2007–2015Based in Kawasaki, JP· patent location history
2012–2015Patents assigned to KANARI KATSUNAO (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 7 | 2007–2015 |
| KANARI KATSUNAOself | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 7 | 2007–2015 |