Inventor
Amitava Majumdar
Inventor
San Jose, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables25%
G11CStatic stores13%
G06FElectric digital data processing11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H01LSemiconductor devices8%
H03KPulse technique4%
H10BElectronic memory devices4%
H10NElectric solid-state devices not otherwise provided for4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G01BMeasuring length, thickness or similar linear dimensions2%
PatentTitleYear
10,872,403System for predicting properties of structures, imager system, and related methods202010,754,759Breakpointing circuitry that evaluates breakpoint conditions while running clock to target circuit202010,756,711Integrated circuit skew determination202010,672,500Non-contact measurement of memory cell threshold voltage202010,650,891Non-contact electron beam probing techniques and related structures202010,621,067Data unit breakpointing circuits and methods202010,403,359Non-contact electron beam probing techniques and related structures201910,381,101Non-contact measurement of memory cell threshold voltage201910,110,234Efficient system debug infrastructure for tiled architecture20189,989,572Method and apparatus for testing interposer dies prior to assembly20189,865,567'Heterogeneous integration of integrated circuit device and companion device'20189,798,352'Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking'20179,761,533'Interposer-less stack die interconnect'20179,600,018'Clock stoppage in integrated circuits with multiple asynchronous clock domains'20179,500,700'Circuits for and methods of testing the operation of an input/output port'20169,453,870'Testing for shorts between internal nodes of a power distribution grid'20168,884,804'Time-to-digital conversion'20148,407,544'Method and apparatus for AC scan testing with distributed capture and shift logic'20137,096,393'Built-in self-test (BIST) of memory interconnect'20067,065,724'Method and apparatus for generating and verifying libraries for ATPG tool'20067,020,820'Instruction-based built-in self-test (BIST) of external memory'20066,813,201'Automatic generation and validation of memory test models'20046,507,925'Spatial and temporal alignment of a scan dump for debug of scan-based designs'20036,263,461'Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit'20016,088,823'Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit'20006,000,050'Method for minimizing ground bounce during DC parametric tests using boundary scan register'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2001Patents assigned to SYNOPSYS INC (3)· patent assignee history
1999–2001Based in Fremont, CA, US· patent location history
2003–2006Patents assigned to SUN MICROSYSTEMS INC (5)· patent assignee history
2003–2020Based in San Jose, CA, US· patent location history
2013Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history
2014–2020Patents assigned to XILINX INC (12)· patent assignee history
2019–2020Patents assigned to MICRON TECHNOLOGY INC (5)· patent assignee history
2019–2020Based in Boise, ID, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 12 | 2014–2020 |
| MICRON TECHNOLOGY INC | 5 | 2019–2020 |
| SUN MICROSYSTEMS INC | 5 | 2003–2006 |
| SYNOPSYS INC | 3 | 1999–2001 |
| ADVANCED MICRO DEVICES INC | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 18 | 2003–2020 |
| Boise, ID, US | 5 | 2019–2020 |
| Fremont, California, US | 3 | 1999–2001 |