Inventor

Yi-Wei Chiu

Inventor

Kaohsiung, TW

Overview

2010–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices28%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

H10DInorganic electric semiconductor devices20%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

H01JElectric discharge tubes or discharge lamps3%

H04LTransmission of digital information, e.g. telegraphic communication2%

G06FElectric digital data processing1%

G11CStatic stores1%

B08BCleaning in general0%

C23CCoating metallic material0%

PatentTitleYear

10,879,051Method for controlling exposure region in bevel etching process for semiconductor fabrication2020 10,879,109Method for forming semiconductor device structure2020 10,861,800Integrated circuit structure having a crown-shaped semiconductor strip and an isolation region recessed in the substrate2020 10,854,603Semiconductor device and method2020 10,847,349Moving focus ring for plasma etcher2020 10,833,914Device or vendor independent network switch management via embedded management controller stack2020 10,825,727Metal gates of transistors having reduced resistivity2020 10,825,739FinFET devices and methods of forming the same2020 10,804,149Self-aligned spacers and method forming same2020 10,770,356Contact structure and method of fabricating the same2020 10,763,162Interconnect structure of semiconductor device2020 10,741,381CMP cleaning system and method2020 10,734,246Heat shield for chamber door and devices manufactured using same2020 10,727,346FinFET device and method of forming2020 10,707,123Etch profile control of interconnect structures2020 10,692,762Semiconductor device with gate stack2020 10,679,891Methods of forming interconnect structures using a vacuum environment2020 10,679,950Methods of forming recesses in substrates by etching dummy Fins2020 10,679,896Contact structure for semiconductor device2020 10,664,551Intuitive user interface (UI) for device or vendor independent network switch management via embedded management controller2020 10,651,079Semiconductor device and manufacturing method thereof2020 10,629,480Method for forming semiconductor device structure2020 10,616,348System and method for providing multiple IPMI serial over LAN (SOL) sessions in management controller stack2020 10,566,232Post-etch treatment of an electrically conductive feature2020 10,529,543Etch process with rotatable shower head2020 10,522,408FinFET device and method of forming same2019 10,510,593Contact openings and methods forming same2019 10,510,516Moving focus ring for plasma etcher2019 10,510,875Source and drain structure with reduced contact resistance and enhanced mobility2019 10,510,596Metal gates of transistors having reduced resistivity2019 10,510,615FinFET devices and methods of forming the same2019 10,510,598Self-aligned spacers and method forming same2019 10,504,738Focus ring for plasma etcher2019 10,504,720Etching using chamber with top plate formed of non-oxygen containing material2019 10,495,970Critical dimension uniformity2019 10,483,165Methods for forming contact plugs with reduced corrosion2019 10,460,995Method of manufacture of a FinFET device2019 10,304,729Method of forming interconnect structures2019 10,297,555Integrated circuit structure having crown-shaped semiconductor strips and recesses in the substrate from etched dummy fins2019 10,290,547Method of manufacturing a semiconductor device with metal gate etch selectivity control2019 10,284,418Network switch management via embedded management controller using management information base (MIB) to JSON parser2019 10,269,938Semiconductor device structure having a doped passivation layer2019 10,269,624Contact plugs and methods of forming same2019 10,269,917Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls2019 10,199,252Thermal pad for etch rate uniformity2019 10,186,456Methods for forming contact plugs with reduced corrosion2019 10,170,555Intermetallic doping film with diffusion in source/drain2019 10,163,650System and method for selective nitride etch2018 10,163,642Semiconductor device, method and tool of manufacture2018 10,163,715FinFET device and method of forming same2018 10,157,782Semiconductor device and manufacturing method thereof2018 10,153,373FinFET device and method of forming2018 10,141,225Metal gates of transistors having reduced resistivity2018 10,121,873Metal gate and contact plug design and method forming same2018 10,083,863Contact structure for semiconductor device2018 10,079,178Formation method of semiconductor device structure using multilayer resist layer2018 10,074,563Structure and formation method of interconnection structure of semiconductor device2018 10,037,918Contact structure and method of fabricating the same2018 10,032,661Semiconductor device, method, and tool of manufacture2018 10,020,379Method for forming semiconductor device structure using double patterning2018 9,972,526Method for forming conductive structure in semiconductor structure2018 9,905,456'Semiconductor device and manufacturing method thereof'2018 9,899,526'Fin-type field effect transistor structure and manufacturing method thereof'2018 9,881,834'Contact openings and methods forming same'2018 9,865,697'Semiconductor device structure and method for forming the same'2018 9,837,539FinFET device and method of forming2017 9,812,363'FinFET device and method of forming same'2017 9,721,805'Formation method of semiconductor device structure'2017 9,543,410'Semiconductor device and formation thereof'2017 9,391,072'Sacrificial oxide with uniform thickness'2016 9,136,109'Sacrificial oxide with uniform thickness'2015 8,837,207'Static memory and memory cell thereof'2014 8,693,237'Single-ended SRAM with cross-point data-aware write operation'2014 8,305,057'Power supply and over voltage protection apparatus and over voltage protection method'2012 8,049,213'Feature dimension measurement'2011 8,010,817'Multi-processor system and performance adjustment method thereof'2011 7,856,108'Method for preventing an output device from being damaged'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2020Based in Taipei, TW· patent location history

2011–2012Patents assigned to ASUSTEK COMP INC (2)· patent assignee history

2011–2020Based in Kaohsiung, TW· patent location history

2012–2014Patents assigned to CHIU YI-WEI (2)· patent assignee history

2014Patents assigned to UNIV NAT CHIAO TUNG (2)· patent assignee history

2014–2019Based in Hsinchu, TW· patent location history

2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (67)· patent assignee history

2020Patents assigned to AMERICAN MEGATRENDS INT LLC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	67	2015–2020
AMERICAN MEGATRENDS INT LLC	3	2020
ASUSTEK COMP INC	2	2011–2012
CHIU YI-WEIself	2	2012–2014
UNIV NAT CHIAO TUNG	2	2014

Locations

Location	Patents	Span
Kaohsiung, TW	67	2011–2020
Taipei, TW	7	2010–2020
Hsinchu, TW	3	2014–2019