Inventor
Jia-Rong Wu
Inventor
Kaohsiung, TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10BElectronic memory devices3%
H01RElectrically-conductive connections1%
H10KOrganic electric solid-state devices1%
PatentTitleYear
10,931,044Board-to-board connector and board-to-board connector assembly202110,643,997Semiconductor device with metal gates202010,141,263Method for fabricating semiconductor device20189,984,974Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer20189,985,020Semiconductor structure and manufacturing method thereof20189,941,215Semiconductor device and method for fabricating the same20189,899,322'Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer'20189,859,170'Method of forming semiconductor structure'20189,831,133Semiconductor devices having metal gate and method for manufacturing semiconductor devices having metal gate20179,754,938'Semiconductor device and method of fabricating the same'20179,685,337'Method for fabricating semiconductor device'20179,660,042'Semiconductor device and manufacturing method thereof'20179,613,969'Semiconductor structure and method of forming the same'20179,564,371'Method for forming semiconductor device'20179,548,239'Method for fabricating contact plug in an interlayer dielectric layer'20179,530,778'Semiconductor devices having metal gate and method for manufacturing semiconductor devices having metal gate'20169,466,521'Semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer'20169,455,227'Semiconductor device and method for fabricating the same'20169,412,745'Semiconductor structure having a center dummy region'20169,337,260'Shallow trench isolation in bulk substrate'20169,324,610'Method for fabricating semiconductor device'20169,312,121'Method for cleaning contact hole and forming contact plug therein'20169,306,032'Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric'20169,263,392'Semiconductor device and method for fabricating the same'20169,230,816'Method for fabricating semiconductor device'20169,117,886'Method for fabricating a semiconductor device by forming and removing a dummy gate structure'20159,006,110'Method for fabricating patterned structure of semiconductor device'20158,962,490'Method for fabricating semiconductor device'20158,928,112'Shallow trench isolation'20158,912,074'Method of forming shallow trench isolations'20148,823,132'Two-portion shallow-trench isolation'20148,765,546'Method for fabricating fin-shaped field-effect transistor'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2020Patents assigned to UNITED MICROELECTRONICS CORP (31)· patent assignee history
2014–2020Based in Kaohsiung, TW· patent location history
2017Based in Kaoshsiung, TW· patent location history
2021Patents assigned to ADVANCED CONNECTEK INC (1)· patent assignee history
2021Based in New Taipei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITED MICROELECTRONICS CORP | 31 | 2014–2020 |
| ADVANCED CONNECTEK INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 30 | 2014–2020 |
| New Taipei, TW | 1 | 2021 |
| Kaoshsiung, TW | 1 | 2017 |