Inventor
Kuan-Cheng Su
Inventor
Taipei, TW
Overview
Patents· 55 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H01LSemiconductor devices25%
H10BElectronic memory devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G01RMeasuring electric variables5%
G11CStatic stores3%
H02HEmergency protective circuit arrangements3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H01JElectric discharge tubes or discharge lamps1%
PatentTitleYear
10,672,759Electrostatic discharge protection semiconductor device202010,629,585Electrostatic discharge protection semiconductor device202010,366,978Grounded gate NMOS transistor having source pulled back region201910,204,897Electrostatic discharge protection semiconductor device201910,103,136Electrostatic discharge protection semiconductor device201810,090,291Electrostatic discharge protection semiconductor device and layout structure of ESD protection semiconductor device201810,068,896Electrostatic discharge protection device and manufacturing method thereof201810,062,751Semiconductor device201810,008,489Electrostatic discharge protection semiconductor device20189,899,369'Layout structure for electrostatic discharge protection'20189,748,222'Fin type electrostatic discharge protection device'20179,691,752'Semiconductor device for electrostatic discharge protection and method of forming the same'20179,673,189'ESD unit'20179,653,450'Electrostatic discharge protection semiconductor device'20179,640,524'Electrostatic discharge protection semiconductor device'20179,607,977'Electrostatic discharge protection device and method for producing an electrostatic discharge protection device'20179,564,436'Semiconductor device'20179,559,091'Method of manufacturing fin diode structure'20179,455,246'Fin diode structure'20169,368,484'Fin type electrostatic discharge protection device'20169,368,500'Complementary metal-oxide-semiconductor device'20169,343,567'Semiconductor device'20169,331,161'Metal gate structure and method of forming the same'20169,331,064'Fin diode structure'20169,093,565'Fin diode structure'20158,963,202'Electrostatic discharge protection apparatus'20158,817,434'Electrostatic discharge (ESD) protection device'20148,711,535'ESD protection circuit and ESD protection device thereof'20148,648,421'Electrostatic discharge (ESD) device and semiconductor structure'20148,510,635'Method for evaluating failure rate'20138,467,162'ESD protection circuit and ESD protection device thereof'20138,283,941'Alternating current (AC) stress test circuit, method for evaluating AC stress induced hot carrier injection (HCI) degradation, and test structure for HCI degradation evaluation'20127,759,957'Method for fabricating a test structure'20107,649,377'Test structure'20107,589,551'On-wafer AC stress test circuit'20096,500,389'Plasma arcing sensor'20026,383,883'Method of reducing junction capacitance of source/drain region'20026,171,899'Method for fabricating a capacitor'20016,093,626'Buried contact method to release plasma-included charging damage on device'20005,918,127'Method of enhancing electrostatic discharge (ESD) protection capability in integrated circuits'19995,859,460'Tri-state read-only memory device and method for fabricating the same'19995,756,376'Method for removing a diffusion barrier layer on pad regions'19985,705,840'Field effect transistor with recessed buried source and drain regions'19985,693,551'Method for fabricating a tri-state read-only memory device'19975,691,234'Buried contact method to release plasma-induced charging damage on device'19975,668,030'Process for making identification alphanumeric code markings for mask ROM devices'19975,665,995'Post passivation programmed mask ROM'19975,597,753'CVD oxide coding method for ultra-high density mask read-only-memory (ROM)'19975,585,297'Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby'19965,576,573'Stacked CVD oxide architecture multi-state memory cell for mask read-only memories'19965,545,580'Multi-state read-only memory using multiple polysilicon selective depositions'19965,536,669'Method for fabricating read-only-memory devices with self-aligned code implants'19965,504,030'Process for fabricating high-density mask ROM devices'19965,429,974'Post passivation mask ROM programming method'19955,382,534'Field effect transistor with recessed buried source and drain regions'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2020Patents assigned to UNITED MICROELECTRONICS CORP (55)· patent assignee history
1995–2020Based in Taipei, TW· patent location history
2009–2014Based in Hsinchu, TW· patent location history
2012–2015Patents assigned to SU KUAN-CHENG (6)· patent assignee history
2013–2015Patents assigned to TANG TIEN-HAO (4)· patent assignee history
2013–2015Patents assigned to WANG CHANG-TZU (4)· patent assignee history
2013Patents assigned to CHEN CHIN-HSIEN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITED MICROELECTRONICS CORP | 55 | 1995–2020 |
| SU KUAN-CHENGself | 6 | 2012–2015 |
| TANG TIEN-HAO | 4 | 2013–2015 |
| WANG CHANG-TZU | 4 | 2013–2015 |
| CHEN CHIN-HSIEN | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 48 | 1995–2020 |
| Hsinchu, TW | 7 | 2009–2014 |