Inventor
Ronald J. Nagahara
Inventor
San Jose, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
B24Bprimary
B24BMachines, devices, or processes for grinding or polishing32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1032%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool3%
B24DTools for grinding, buffing or sharpening3%
C25FProcesses for the electrolytic removal of materials from objects3%
PatentTitleYear
6,951,808'Metal planarization system'20056,752,916'Electrochemical planarization end point detection'20046,713,394'Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures'20046,607,967'Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate'20036,586,326'Metal planarization system'20036,531,397'Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing'20036,503,828'Process for selective polishing of metal-filled trenches of integrated circuit structures'20036,489,242'Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures'20026,417,093'Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing'20026,372,524'Method for CMP endpoint detection'20026,179,956'Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing'20016,168,508'Polishing pad surface for improved process control'20016,114,215'Generating non-planar topology on the surface of planar and near-planar substrates'20006,106,371'Effective pad conditioning'20006,074,288'Modified carrier films to produce more uniformly polished substrate surfaces'20006,066,266'In-situ chemical-mechanical polishing slurry formulation for compensation of polish pad degradation'20005,961,375'Shimming substrate holder assemblies to produce more uniformly polished substrate surfaces'19995,944,585'Use of abrasive tape conveying assemblies for conditioning polishing pads'19995,941,761'Shaping polishing pad to control material removal rate selectively'19995,931,719'Method and apparatus for using pressure differentials through a polishing pad to improve performance in chemical mechanical polishing'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2005Patents assigned to LSI LOGIC CORP (20)· patent assignee history
1999–2005Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 20 | 1999–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 20 | 1999–2005 |