Inventor
Billy Wayne Garrett, Jr.
Inventor
Mountain View, CA, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores35%
G06FElectric digital data processing33%
H04LTransmission of digital information, e.g. telegraphic communication15%
H03KPulse technique9%
H05KPrinted circuits5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
PatentTitleYear
10,860,216Mechanism for enabling full data bus utilization without increasing data granularity202010,146,445Mechanism for enabling full data bus utilization without increasing data granularity20189,998,305Multi-PAM output driver with distortion compensation20189,544,169'Multiphase receiver with equalization circuitry'20179,417,800'Mechanism for enabling full data bus utilization without increasing data granularity'20169,257,161'Mechanism for enabling full data bus utilization without increasing data granularity'20168,856,480'Mechanism for enabling full data bus utilization without increasing data granularity'20148,634,452'Multiphase receiver with equalization circuitry'20148,370,596'Mechanism for enabling full data bus utilization without increasing data granularity'20138,199,859'Integrating receiver with precharge circuitry'20127,809,088'Multiphase receiver with equalization'20107,626,442'Low latency multi-level communication interface'20097,536,494'Expandable slave device system with buffered subsystems'20097,500,075'Mechanism for enabling full data bus utilization without increasing data granularity'20097,352,234'Current control technique'20087,222,209'Expandable slave device system'20077,170,314'Multiple channel modules and bus systems using same'20077,167,039'Memory device having an adjustable voltage swing setting'20077,124,221'Low latency multi-level communication interface'20067,039,782'Memory system with channel multiplexing of multiple memory devices'20066,975,159'Method of operation in a system having a memory device having an adjustable output voltage setting'20056,975,160'System including an integrated circuit memory device having an adjustable output voltage setting'20056,898,085'Multiple channel modules and bus systems using same'20056,870,419'Memory system including a memory device having a controlled output driver characteristic'20056,839,266'Memory module with offset data lines and bit line swizzle configuration'20056,765,800'Multiple channel modules and bus systems using same'20046,708,248'Memory system with channel multiplexing of multiple memory devices'20046,687,780'Expandable slave device system'20046,608,507'Memory system including a memory device having a controlled output driver characteristic'20036,556,052'Semiconductor controller device having a controlled output driver characteristic'20036,462,591'Semiconductor memory device having a controlled output driver characteristic'20026,370,668'High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes'20026,294,934'Current control technique'20016,266,730'High-frequency bus system'20016,094,075'Current control technique'20006,067,594'High frequency bus system'20005,956,284'Method and apparatus for writing to memory components'19995,940,340'Method and apparatus for writing to memory components'19995,844,855'Method and apparatus for writing to memory components'19985,764,963'Method and apparatus for performing maskable multiple color block writes'19985,680,361'Method and apparatus for writing to memory components'19975,511,024'Dynamic random access memory system'19965,434,817'Dynamic random access memory system'19955,430,676'Dynamic random access memory system'19954,987,551'Apparatus for creating a cursor pattern by strips related to individual scan lines'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991Based in Columbia, SC, US· patent location history
1995–2020Patents assigned to RAMBUS INC (44)· patent assignee history
1995–2014Based in Mountain View, CA, US· patent location history
2012–2014Patents assigned to CHAU PAK S (2)· patent assignee history
2012–2014Patents assigned to DONNELLY KEVIN S (2)· patent assignee history
2012–2014Patents assigned to GARLEPP BRUNO W (2)· patent assignee history
2012–2014Patents assigned to GARRETT JR BILLY W (2)· patent assignee history
2016–2020Based in North Charleston, SC, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 44 | 1995–2020 |
| CHAU PAK S | 2 | 2012–2014 |
| DONNELLY KEVIN S | 2 | 2012–2014 |
| GARLEPP BRUNO W | 2 | 2012–2014 |
| GARRETT JR BILLY Wself | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 38 | 1995–2014 |
| North Charleston, SC, US | 6 | 2016–2020 |
| Columbia, SC, US | 1 | 1991 |