Inventor

Dale W. Collins

Inventor

Boise, ID, US

Overview

44→

Patents

2004–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

H01LSemiconductor devices14%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

H10BElectronic memory devices11%

H10NElectric solid-state devices not otherwise provided for11%

H10DInorganic electric semiconductor devices8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

G11CStatic stores4%

C25DProcesses for the electrolytic or electrophoretic production of coatings3%

H01BCables2%

PatentTitleYear

10,879,113Semiconductor constructions; and methods for providing electrically conductive material within openings2020 10,680,175Memory structures having improved write endurance2020 10,490,740Non-volatile memory system with reliability enhancement mechanism and method of manufacture thereof2019 10,347,831Doping of selector and storage materials of a memory cell2019 10,256,406Semiconductor structures including liners and related methods2019 10,121,697Semiconductor constructions; and methods for providing electrically conductive material within openings2018 10,090,462Resistive memory devices2018 10,008,665Doping of selector and storage materials of a memory cell2018 9,553,264'Memory cells and semiconductor structures including electrodes comprising a metal, and related methods'2017 9,444,042'Memory cells and methods of forming memory cells'2016 9,431,606'Memory cells'2016 9,419,212'Barrier film techniques and configurations for phase-change memory elements'2016 9,224,945'Resistive memory devices'2015 9,209,388'Memory cells and methods of forming memory cells'2015 9,177,917'Semiconductor constructions'2015 9,093,636'Incorporation of oxygen into memory cells'2015 9,048,415'Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods'2015 9,006,702'Semiconductor structure including a zirconium oxide material'2015 8,859,382'Methods of forming metal oxide and memory cells'2014 8,637,846'Semiconductor structure including a zirconium oxide material'2014 8,603,318'Method of selectively removing conductive material'2013 7,935,242'Method of selectively removing conductive material'2011 7,700,478'Intermediate anneal for metal deposition'2010 7,666,776'Methods of forming conductive structures'2010 7,498,670'Semiconductor structures having electrophoretically insulated vias'2009 7,446,415'Method for filling electrically different features'2008 7,405,007'Semiconductor having a substantially uniform layer of electroplated metal'2008 7,375,014'Methods of electrochemically treating semiconductor substrates'2008 7,348,234'Methods of forming capacitor constructions'2008 7,344,977'Method of electroplating a substance over a semiconductor substrate'2008 7,335,981'Methods for creating electrophoretically insulated vias in semiconductive substrates'2008 7,282,131'Methods of electrochemically treating semiconductor substrates'2007 7,273,778'Method of electroplating a substance over a semiconductor substrate'2007 7,192,495'Intermediate anneal for metal deposition'2007 7,179,716'Method of forming a metal-containing layer over selected regions of a semiconductor substrate'2007 7,179,361'Method of forming a mass over a semiconductor substrate'2007 7,105,437'Methods for creating electrophoretically insulated vias in semiconductive substrates'2006 7,105,921'Semiconductor assemblies having electrophoretically insulated vias'2006 7,098,128'Method for filling electrically different features'2006 7,030,010'Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures'2006 7,025,866'Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces'2006 7,001,492'Systems for electroplating metal onto a layer of low conductivity material'2006 6,984,301'Methods of forming capacitor constructions'2006 6,723,219'Method of direct electroplating on a low conductivity material, and electroplated metal deposited therewith'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2020Patents assigned to MICRON TECHNOLOGY INC (39)· patent assignee history

2004–2020Based in Boise, ID, US· patent location history

2013–2015Patents assigned to COLLINS DALE W (7)· patent assignee history

2014–2015Patents assigned to LENGADE SWAPNIL (2)· patent assignee history

2014Patents assigned to RAMASWAMY D V NIRMAL (2)· patent assignee history

2016–2020Patents assigned to INTEL CORP (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	39	2004–2020
COLLINS DALE Wself	7	2013–2015
INTEL CORP	4	2016–2020
LENGADE SWAPNIL	2	2014–2015
RAMASWAMY D V NIRMAL	2	2014

Locations

Location	Patents	Span
Boise, ID, US	44	2004–2020