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Inventor

Jean-François Côté

Inventor
Chelsea, CA

Overview

38→
Patents
1998–2021
Patent span
Physics
Primary field (CPC G)

Patents· 38 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary
G01RMeasuring electric variables45%
G06FElectric digital data processing27%
G11CStatic stores14%
H04LTransmission of digital information, e.g. telegraphic communication7%
G06TImage data processing or generation, in general4%
H04NPictorial communication, e.g. television4%
PatentTitleYear
11,085,965Clock gating and scan clock generation for circuit test202111,042,181Local clock injection and independent capture for circuit test of multiple cores in clock mesh architecture202110,788,530Efficient and flexible network for streaming data in circuits202010,775,436Streaming networks efficiency using data throttling202010,473,721Data streaming for testing identical circuit blocks201910,476,740Data generation for streaming networks in circuits20199,389,944'Test access architecture for multi-die circuits'20169,389,945'Test access architecture for stacked dies'20168,619,077'Efficient execution of color space processing functions in a graphics processing unit'20138,516,317'Methods for at-speed testing of memory interface'20137,757,135'Method and apparatus for storing and distributing memory repair information'20107,617,425'Method for at-speed testing of memory interface using scan'20097,424,656'Clocking methodology for at-speed testing of scan circuits with synchronous clocks'20087,370,251'Method and circuit for collecting memory failure information'20087,155,651'Clock controller for at-speed testing of scan circuits'20067,129,962'Efficient video processing method and system'20067,103,860'Verification of embedded test structures in circuit designs'20066,952,211'Motion compensation using shared resources of a graphics processor unit'20056,868,532'Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby'20056,829,730'Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same'20046,763,489'Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description'20046,760,874'Test access circuit and method of accessing embedded test controllers in integrated circuit modules'20046,738,938'Method for collecting failure information for a memory using an embedded test controller'20046,725,435'Method and program product for completing a circuit design having embedded test structures'20046,678,875'Self-contained embedded test design environment and environment setup utility'20046,671,839'Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith'20036,615,392'Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby'20036,614,263'Method and circuitry for controlling clocks of embedded blocks during logic bist test mode'20036,536,008'Fault insertion method, boundary scan cells, and integrated circuit for use therewith'20036,510,534'Method and apparatus for testing high performance circuits'20036,330,681'Method and apparatus for controlling power level during BIST'20016,327,684'Method of testing at-speed circuits having asynchronous clocks and controller for use therewith'20016,145,105'Method and apparatus for scan testing digital circuits'20006,115,827'Clock skew management method and apparatus'20006,046,946'Method and apparatus for testing multi-port memory using shadow read'20006,000,051'Method and apparatus for high-speed interconnect testing'19995,900,753'Asynchronous interface'19995,812,469'Method and apparatus for testing multi-port memory'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2003Patents assigned to LOGIC VISION INC (4)· patent assignee history
1998–2001Based in Aylmer, CA· patent location history
1999–2009Patents assigned to LOGICVISION INC (21)· patent assignee history
2003–2010Based in Chelsea, CA· patent location history
2005–2013Patents assigned to MATROX GRAPHICS INC (3)· patent assignee history
2005–2013Based in Boucherville, CA· patent location history
2010–2021Patents assigned to MENTOR GRAPHICS CORP (10)· patent assignee history
2013Patents assigned to COTE JEAN-FRANCOIS (2)· patent assignee history
2013–2020Based in Gatineau, CA· patent location history
2021Based in Davie, FL, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LOGICVISION INC211999–2009
MENTOR GRAPHICS CORP102010–2021
LOGIC VISION INC41998–2003
MATROX GRAPHICS INC32005–2013
COTE JEAN-FRANCOISself22013
Locations
LocationPatentsSpan
Chelsea, CA172003–2010
Aylmer, CA81998–2001
Gatineau, CA52013–2020
Boucherville, CA32005–2013
Davie, Florida, US22021