Inventor
Sridhar P. Subramanian
Inventor
Cupertino, CA, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing51%
H04LTransmission of digital information, e.g. telegraphic communication19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
G01RMeasuring electric variables5%
G11CStatic stores5%
H03MCoding3%
H04BTransmission3%
H03KPulse technique2%
H04WWireless communication networks2%
PatentTitleYear
10,673,850Network authorization in web-based or single sign-on authentication environments202010,592,461Extremely high frequency systems and methods of operating the same to establish USB data transport protocols202010,462,007Network address transparency through user role authentication201910,003,569Network resource sharing for routing and forwarding information20189,940,295Extremely high frequency systems and methods of operating the same to establish USB data transport protocols20189,680,751'Methods and devices for providing service insertion in a TRILL network'20179,648,005'Method and system for extending network resources campus-wide based on user role and location'20179,641,462'Accelerating network convergence for layer 3 roams in a next generation network closet campus'20179,590,906'Network resource sharing for routing and forwarding information'20179,369,473'Method and system for extending network resources campus-wide based on user role and location'20169,049,127'Methods and devices for providing service clustering in a trill network'20158,743,653'Reducing dynamic power consumption of a memory circuit'20148,503,264'Reducing power consumption in a segmented memory'20138,423,935'Method and apparatus for verifying output-based clock gating'20138,359,414'Retry mechanism'20138,347,040'Latency reduction for cache coherent bus-based cache'20138,307,236'Oversampling-based scheme for synchronous interface communication'20128,301,941'Memory controller with loopback test interface'20128,219,880'Combined single error correction/device kill detection code'20128,219,946'Method for clock gating circuits'20128,099,703'Method and system for verifying power-optimized electronic designs using equivalency checking'20128,086,915'Memory controller with loopback test interface'20118,055,975'Combined single error correction/device kill detection code'20117,991,928'Retry mechanism'20117,970,970'Non-blocking address switch with shallow per agent queues'20117,949,832'Latency reduction for cache coherent bus-based cache'20117,836,372'Memory controller with loopback test interface'20107,836,324'Oversampling-based scheme for synchronous interface communication'20107,752,366'Non-blocking address switch with shallow per agent queues'20107,746,116'Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis'20107,702,858'Latency reduction for cache coherent bus-based cache'20107,586,911'Method and apparatus for packet transmit queue control'20097,529,866'Retry mechanism in cache coherent communication among agents'20097,471,682'Method and apparatus for providing internal table extensibility based on product configuration'20087,461,190'Non-blocking address switch with shallow per agent queues'20087,426,601'Segmented interconnect for connecting multiple agents in a system'20087,398,361'Combined buffer for snoop, store merging, load miss, and writeback operations'20087,269,682'Segmented interconnect for connecting multiple agents in a system'20076,741,258'Distributed translation look-aside buffers for graphics address remapping table'20046,686,920'Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer'20046,624,681'Circuit and method for stopping a clock tree while maintaining PLL lock'20036,601,182'Optimized static sliding-window for ACK sampling'20036,571,318'Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism'20036,449,759'System and method for automatic insertion and placement of repeater buffers on an integrated circuit floor plan'20026,345,328'Gear box for multiple clock domains'20026,173,378'Method for ordering a request for access to a system memory using a reordering buffer or FIFO'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2004Patents assigned to ADVANCED MICRO DEVICES INC (8)· patent assignee history
2001–2009Based in Sunnyvale, CA, US· patent location history
2007–2020Based in Cupertino, CA, US· patent location history
2010–2013Patents assigned to APPLE INC (14)· patent assignee history
2010–2014Patents assigned to XILINX INC (6)· patent assignee history
2011–2013Patents assigned to SUBRAMANIAN SRIDHAR P (6)· patent assignee history
2015–2020Patents assigned to CISCO TECH INC (9)· patent assignee history
2015–2017Based in San Jose, CA, US· patent location history
2016–2020Based in Fremont, CA, US· patent location history
2018Based in Campbell, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLE INC | 14 | 2010–2013 |
| CISCO TECH INC | 9 | 2015–2020 |
| ADVANCED MICRO DEVICES INC | 8 | 2001–2004 |
| SUBRAMANIAN SRIDHAR Pself | 6 | 2011–2013 |
| XILINX INC | 6 | 2010–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 26 | 2007–2020 |
| Sunnyvale, California, US | 10 | 2001–2009 |
| Fremont, California, US | 7 | 2016–2020 |
| San Jose, California, US | 2 | 2015–2017 |
| Campbell, California, US | 1 | 2018 |