Inventor
Ko-Min Chang
Inventor
Austin, TX, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices24%
H10BElectronic memory devices23%
G11CStatic stores15%
H01LSemiconductor devices8%
B82YSpecific uses or applications of nanostructures7%
H10NElectric solid-state devices not otherwise provided for6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G01PMeasuring linear or angular speed, acceleration, deceleration, or shock1%
G01VGeophysics1%
PatentTitleYear
10,095,186User interface activation20189,620,604'Structures for split gate memory cell scaling with merged control gates'20179,425,055'Split gate memory cell with a layer of nanocrystals with improved erase performance'20169,318,501'Methods and structures for split gate memory cell scaling with merged control gates'20169,136,360'Methods and structures for charge storage isolation in split-gate memory arrays'20159,114,980'Field focusing features in a ReRAM cell'20159,118,008'Field focusing features in a ReRAM cell'20158,962,385'ReRAM device structure'20158,921,155'Resistive random access memory (RAM) cell and method for forming'20148,860,001'ReRAM device structure'20148,835,295'Split gate memory device with gap spacer'20148,779,405'Field focusing features in a ReRAM cell'20148,173,505'Method of making a split gate memory cell'20127,955,877'Method for simulating long-term performance of a non-volatile memory by exposing the non-volatile memory to heavy-ion radiation'20117,811,886'Split-gate thin film storage NVM cell with reduced load-up/trap-up effects'20107,700,439'Silicided nonvolatile memory and method of making same'20107,619,275'Process for forming an electronic device including discontinuous storage elements'20097,582,929'Electronic device including discontinuous storage elements'20097,524,719'Method of making self-aligned split gate memory cell'20097,521,317'Method of forming a semiconductor device and structure thereof'20097,341,914'Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate'20086,939,767'Multi-bit non-volatile integrated circuit memory and method therefor'20056,844,588'Non-volatile memory'20056,791,883'Program and erase in a thin film storage non-volatile memory'20045,969,383'Split-gate memory device and method for accessing the same'19995,949,706'Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line'19995,898,619'Memory cell having a plural transistor transmission gate and method of formation'19995,731,238'Integrated circuit having a jet vapor deposition silicon nitride film and method of making the same'19985,705,415'Process for forming an electrically programmable read-only memory cell'19985,706,228'Method for operating a memory array'19985,646,060'Method for making an EEPROM cell with isolation transistor'19975,633,186'Process for fabricating a non-volatile memory cell in a semiconductor device'19975,605,855'Process for fabricating a graded-channel MOS device'19975,474,947'Nonvolatile memory process'19955,471,422'EEPROM cell with isolation transistor and methods for making and operating the same'19955,467,308'Cross-point eeprom memory array'19955,422,846'Nonvolatile memory having overerase protection'19955,357,476'Apparatus and method for erasing a flash EEPROM'19945,273,923'Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions'19935,258,949'Nonvolatile memory with enhanced carrier generation and method for programming the same'19935,130,769'Nonvolatile memory cell'19925,103,425'Zener regulated programming circuit for a nonvolatile memory'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–1999Patents assigned to MOTOROLA INC (17)· patent assignee history
1992–2017Based in Austin, TX, US· patent location history
2004–2017Patents assigned to FREESCALE SEMICONDUCTOR INC (23)· patent assignee history
2012–2016Patents assigned to CHANG KO-MIN (10)· patent assignee history
2014–2015Patents assigned to HONG CHEONG MIN (5)· patent assignee history
2014–2015Patents assigned to ZHOU FENG (5)· patent assignee history
2018Based in Heeze, NL· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 23 | 2004–2017 |
| MOTOROLA INC | 17 | 1992–1999 |
| CHANG KO-MINself | 10 | 2012–2016 |
| HONG CHEONG MIN | 5 | 2014–2015 |
| ZHOU FENG | 5 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 41 | 1992–2017 |
| Heeze, NL | 1 | 2018 |