Inventor

Prasanna Khare

Inventor

Schenectady, NY, US

Overview

2012–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 45 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices33%

H01LSemiconductor devices29%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

H10BElectronic memory devices5%

H04LTransmission of digital information, e.g. telegraphic communication1%

PatentTitleYear

11,128,442System for cryptographic hash-based user authentication in a distributed register network2021 10,580,771Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods2020 10,340,195Method to co-integrate SiGe and Si channels for finFET devices2019 10,170,546Fully substrate-isolated FinFET transistor2019 10,170,475Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region2019 10,134,899Facet-free strained silicon transistor2018 10,134,895Facet-free strained silicon transistor2018 10,062,690Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods2018 10,038,075Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region2018 9,991,351Method of making a semiconductor device using a dummy gate2018 9,905,662'Method of making a semiconductor device using a dummy gate'2018 9,893,147'Fully substrate-isolated FinFET transistor'2018 9,847,260Method to co-integrate SiGe and Si channels for finFET devices2017 9,793,378'Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability'2017 9,768,055'Isolation regions for SOI devices'2017 9,685,380'Method to co-integrate SiGe and Si channels for finFET devices'2017 9,673,222'Fin isolation structures facilitating different fin isolation schemes'2017 9,620,507'Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region'2017 9,620,506'Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region'2017 9,520,393'Fully substrate-isolated FinFET transistor'2016 9,502,292'Dual shallow trench isolation liner for preventing electrical shorts'2016 9,437,504'Method for the formation of fin structures for FinFET devices'2016 9,419,111'Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods'2016 9,349,730'Fin transformation process and isolation structures facilitating different Fin isolation schemes'2016 9,252,052'Dual shallow trench isolation liner for preventing electrical shorts'2016 9,171,757'Dual shallow trench isolation liner for preventing electrical shorts'2015 9,166,023'Bulk finFET semiconductor-on-nothing integration'2015 9,123,809'Transistor having a stressed body'2015 9,099,570'Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices'2015 9,093,496'Process for faciltiating fin isolation schemes'2015 9,093,556'Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods'2015 9,082,788'Method of making a semiconductor device including an all around gate'2015 9,012,999'Semiconductor device with an inclined source/drain and associated methods'2015 9,006,816'Memory device having multiple dielectric gate stacks and related methods'2015 9,000,491'Layer formation with reduced channel loss'2015 9,000,555'Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods'2015 8,987,082'Method of making a semiconductor device using sacrificial fins'2015 8,956,942'Method of forming a fully substrate-isolated FinFET transistor'2015 8,860,123'Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods'2014 8,828,851'Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering'2014 8,796,147'Layer formation with reduced channel loss'2014 8,759,874'FinFET device with isolated channel'2014 8,703,550'Dual shallow trench isolation liner for preventing electrical shorts'2014 8,237,229'Method and apparatus for buried-channel semiconductor device'2012 8,187,975'Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2020Patents assigned to ST MICROELECTRONICS INC (43)· patent assignee history

2012–2017Patents assigned to KHARE PRASANNA (9)· patent assignee history

2012–2017Patents assigned to LIU QING (8)· patent assignee history

2012–2017Patents assigned to LOUBET NICOLAS (8)· patent assignee history

2012–2020Based in Schenectady, NY, US· patent location history

2012Based in Phoenix, AZ, US· patent location history

2014–2019Patents assigned to IBM (17)· patent assignee history

2021Based in Maharashtra, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ST MICROELECTRONICS INC	43	2012–2020
IBM	17	2014–2019
KHARE PRASANNAself	9	2012–2017
LIU QING	8	2012–2017
LOUBET NICOLAS	8	2012–2017

Locations

Location	Patents	Span
Schenectady, New York, US	43	2012–2020
Maharashtra, IN	1	2021
Phoenix, AZ, US	1	2012