Inventor

Pavel Poplevine

Inventor

Foster City, CA, US

Overview

1998–2013

Patent span

Physics

Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores53%

H10DInorganic electric semiconductor devices16%

H10BElectronic memory devices10%

G06FElectric digital data processing6%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%

G05FSystems for regulating electric or magnetic variables2%

H03MCoding2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

RE044130'Anti-pirate circuit for protection against commercial integrated circuit pirates'2013 8,363,469'All-NMOS 4-transistor non-volatile memory cell'2013 8,284,600'5-transistor non-volatile memory cell'2012 8,213,227'4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure'2012 8,159,877'Method of directly reading output voltage to determine data stored in a non-volatile memory cell'2012 7,656,698'Non-volatile memory cell with improved programming technique with decoupling pass gates and equalize transistors'2010 7,602,641'Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure'2009 7,558,969'Anti-pirate circuit for protection against commercial integrated circuit pirates'2009 7,453,726'Non-volatile memory cell with improved programming technique and density'2008 7,286,383'Bit line sharing and word line load reduction for low AC power SRAM architecture'2007 7,239,558'Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle'2007 7,206,959'Closed-loop, supply-adjusted ROM memory circuit'2007 7,167,392'Non-volatile memory cell with improved programming technique'2007 7,164,606'Reverse fowler-nordheim tunneling programming for non-volatile memory cell'2007 7,126,866'Low power ROM architecture'2006 7,069,461'Closed-loop, supply-adjusted RAM memory circuit'2006 7,061,792'Low AC power SRAM architecture'2006 7,042,763'Programming method for nonvolatile memory cell'2006 7,020,027'Programming method for nonvolatile memory cell'2006 6,992,927'Nonvolatile memory cell'2006 6,985,386'Programming method for nonvolatile memory cell'2006 6,711,051'Static RAM architecture with bit line partitioning'2004 6,642,587'High density ROM architecture'2003 6,621,736'Method of programming a splity-gate flash memory cell with a positive inhibiting word line voltage'2003 6,618,282'High density ROM architecture with inversion of programming'2003 6,563,730'Low power static RAM architecture'2003 6,525,397'Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology'2003 6,420,217'Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology'2002 6,384,398'CMOS compatible pixel cell that utilizes a gated diode to reset the cell'2002 6,380,571'CMOS compatible pixel cell that utilizes a gated diode to reset the cell'2002 6,380,054'Schottky diode with reduced size'2002 6,285,590'Low power consumption semiconductor ROM, EPROM, EEPROM and like circuit'2001 6,262,460'Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor'2001 6,229,739'Sense amplifier having a bias circuit with a reduced size'2001 6,218,866'Semiconductor device for prevention of a floating gate condition on an input node of a MOS logic circuit and a method for its manufacture'2001 6,218,688'Schottky diode with reduced size'2001 6,184,557'I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection'2001 6,169,310'Electrostatic discharge protection device'2001 6,122,204'Sense amplifier having a bias circuit with a reduced size'2000 6,078,211'Substrate biasing circuit that utilizes a gated diode to set the bias on the substrate'2000 6,078,094'Starter current source device with automatic shut-down capability and method for its manufacture'2000 6,049,202'Reference current generator with gated-diodes'2000 6,031,275'Antifuse with a silicide layer overlying a diffusion region'2000 5,982,676'Low voltage generator for bitlines'1999 5,978,269'Apparatus and method for lowering the potential barrier across the source-to-well junction during the programming of non-volatile memory cells'1999 5,721,545'Methods and apparatus for serial-to-parallel and parallel-to-serial conversion'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998Based in Santa Cruz, CA, US· patent location history

1999–2013Patents assigned to NAT SEMICONDUCTOR CORP (44)· patent assignee history

1999–2013Based in Foster City, CA, US· patent location history

2012–2013Patents assigned to POPLEVINE PAVEL (5)· patent assignee history

2012–2013Patents assigned to FRANKLIN ANDREW J (4)· patent assignee history

2012–2013Patents assigned to LIN HENGYANG JAMES (4)· patent assignee history

2012Patents assigned to HO ERNES (3)· patent assignee history

2012–2013Based in Burlingame, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
NAT SEMICONDUCTOR CORP	44	1999–2013
POPLEVINE PAVELself	5	2012–2013
FRANKLIN ANDREW J	4	2012–2013
LIN HENGYANG JAMES	4	2012–2013
HO ERNES	3	2012

Locations

Location	Patents	Span
Foster City, California, US	41	1999–2013
Burlingame, California, US	4	2012–2013
Santa Cruz, California, US	1	1998