Inventor

Donald F. Hooper

Inventor

Shrewsbury, MA, US

Overview

63→

Patents

1987–2014

Patent span

Physics

Primary field (CPC G)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing48%

H04LTransmission of digital information, e.g. telegraphic communication30%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests14%

H04NPictorial communication, e.g. television5%

G06NComputing arrangements based on specific computational models1%

G11BInformation storage based on relative movement between record carrier and transducer1%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%

PatentTitleYear

8,713,569'Dynamic association and disassociation of threads to device functions based on requestor identification'2014 7,991,983'Register set used in multithreaded parallel processor architecture'2011 7,751,402'Method and apparatus for gigabit packet assignment for multithreaded packet processing'2010 7,684,970'Graphical user interface for use during processor simulation'2010 7,546,444'Register set used in multithreaded parallel processor architecture'2009 7,515,588'Method and apparatus to support a large internet protocol forwarding information base'2009 7,480,706'Multi-threaded round-robin receive for fast network port'2009 7,477,641'Providing access to data shared by packet processing threads'2009 7,471,688'Scheduling system for transmission of cells to ATM virtual circuits and DSL ports'2008 7,443,836'Processing a data packet'2008 7,441,245'Phasing for a multi-threaded network processor'2008 7,434,221'Multi-threaded sequenced receive for fast network port stream of packets'2008 7,433,307'Flow control in a network environment'2008 7,421,572'Branch instruction for processor with branching dependent on a specified bit in a register'2008 7,391,772'Network multicasting'2008 7,352,769'Multiple calendar schedule reservation structure and method'2008 7,343,563'Graphical user interface'2008 7,336,606'Circular link list scheduling'2008 7,328,429'Instruction operand tracing for software debug'2008 7,289,455'Network statistics'2007 7,248,584'Network packet processing'2007 7,240,164'Folding for a multi-threaded network processor'2007 7,206,858'DSL transmit traffic shaper structure and procedure'2007 7,191,309'Double shift instruction for micro engine used in multithreaded parallel processor architecture'2007 7,191,321'Microengine for parallel processor architecture'2007 7,181,742'Allocation of packets and threads'2007 7,158,964'Queue management'2007 7,126,952'Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method'2006 7,124,196'Processing a network packet using queues'2006 7,111,296'Thread signaling in multi-threaded processor'2006 7,111,071'Longest prefix match for IP routers'2006 7,100,102'Method and apparatus for performing cyclic redundancy checks'2006 7,096,277'Distributed lookup based on packet contents'2006 7,082,104'Network device switch'2006 7,020,871'Breakpoint method for parallel hardware threads in multithreaded processor'2006 7,016,826'Apparatus and method of developing software for a multi-processor chip'2006 7,006,495'Transmitting multicast data packets'2006 6,952,824'Multi-threaded sequenced receive for fast network port stream of packets'2005 6,947,425'Multi-threaded sequenced transmit software for packet forwarding device'2005 6,944,850'Hop method for stepping parallel hardware threads'2005 6,823,438'Method for memory allocation and management using push/pop apparatus'2004 6,684,395'Multiple image dynamic bind and load procedure for a multi-processor'2004 6,668,311'Method for memory allocation and management using push/pop apparatus'2003 6,668,317'Microengine for parallel processor architecture'2003 6,661,794'Method and apparatus for gigabit packet assignment for multithreaded packet processing'2003 6,625,654'Thread signaling in multi-threaded network processor'2003 6,611,276'Graphical user interface that displays operation of processor threads over time'2003 5,819,282'Database generator'1998 5,671,225'Distributed interactive multimedia service system'1997 5,493,638'Remote display of an image by transmitting compressed video frames representing back-ground and overlay portions thereof'1996 5,452,226'Rule structure for insertion of new elements in a circuit design synthesis procedure'1995 5,442,390'Video on demand with memory accessing and or like functions'1995 5,422,674'Remote display of an image by transmitting compressed video frames representing background and overlay portions thereof'1995 5,414,455'Segmented video on demand system'1995 5,267,175'Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design'1993 5,222,029'Bitwise implementation mechanism for a circuit design synthesis procedure'1993 5,212,650'Procedure and data structure for synthesis and transformation of logic circuit designs'1993 5,175,696'Rule structure in a procedure for synthesis of logic circuits'1992 5,168,455'Procedure for incorporating timing parameters in the synthesis of logic circuit designs'1992 5,151,867'Method of minimizing sum-of-product cases in a heterogeneous data base environment for circuit synthesis'1992 5,150,308'Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs'1992 4,794,527'Microprogrammed data processing system using latch circuits to access different control stores with the same instruction at different times'1988 4,689,765'Groups of tag signals for data store in multi-plane set of buffers'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–1998Patents assigned to DIGITAL EQUIPMENT CORP (16)· patent assignee history

1987–2014Based in Shrewsbury, MA, US· patent location history

1988–1995Based in Northboro, MA, US· patent location history

1992Based in Northborough, MA, US· patent location history

2003–2014Patents assigned to INTEL CORP (47)· patent assignee history

2007Based in Santa Clara, CA, US· patent location history

2014Patents assigned to BARRY PETER (1)· patent assignee history

2014Patents assigned to HOOPER DONALD F (1)· patent assignee history

2014Patents assigned to MOSUR PRAVEEN (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	47	2003–2014
DIGITAL EQUIPMENT CORP	16	1987–1998
BARRY PETER	1	2014
HOOPER DONALD Fself	1	2014
MOSUR PRAVEEN	1	2014

Locations

Location	Patents	Span
Shrewsbury, Massachusetts, US	53	1987–2014
Northboro, Massachusetts, US	7	1988–1995
Northborough, Massachusetts, US	2	1992
Santa Clara, California, US	1	2007