Inventor
Ramakrishna K. Tanikella
Inventor
Hyderabad, IN
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique48%
G06FElectric digital data processing17%
G01RMeasuring electric variables10%
H01LSemiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
10,998,904Programmable termination circuits for programmable devices202110,804,255Circuit for and method of transmitting a signal in an integrated circuit device202010,503,861Placing and routing an interface portion and a main portion of a circuit design20199,054,684'Single event upset enhanced architecture'20159,000,529'Reduction of single event upsets within a semiconductor integrated circuit'20158,933,447'Method and apparatus for programmable device testing in stacked die applications'20158,120,382'Programmable integrated circuit with mirrored interconnect structure'20128,001,511'Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies'20117,743,175'Methods of initializing routing structures in integrated circuits'20107,548,089'Structures and methods to avoiding hold time violations in a programmable logic device'20097,451,421'Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies'20087,382,157'Interconnect driver circuits for dynamic logic'20087,312,631'Structures and methods for avoiding hold time violations in a programmable logic device'20077,199,610'Integrated circuit interconnect structure having reduced coupling between interconnect lines'20077,075,332'Six-input look-up table and associated memory control circuitry for use in a field programmable gate array'20067,061,271'Six-input look-up table for use in a field programmable gate array'20066,933,747'Structures and methods of testing interconnect structures in programmable logic devices'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2021Patents assigned to XILINX INC (17)· patent assignee history
2005–2008Based in Boulder, CO, US· patent location history
2008–2009Based in Thornton, CO, US· patent location history
2010–2011Based in Longmont, CO, US· patent location history
2012–2015Patents assigned to BAUER TREVOR J (2)· patent assignee history
2012–2015Patents assigned to TANIKELLA RAMAKRISHNA K (2)· patent assignee history
2012–2015Patents assigned to YOUNG STEVEN P (2)· patent assignee history
2012–2021Based in Hyderabad, IN· patent location history
2015Patents assigned to GAIDE BRIAN C (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 17 | 2005–2021 |
| BAUER TREVOR J | 2 | 2012–2015 |
| TANIKELLA RAMAKRISHNA Kself | 2 | 2012–2015 |
| YOUNG STEVEN P | 2 | 2012–2015 |
| GAIDE BRIAN C | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hyderabad, IN | 7 | 2012–2021 |
| Boulder, CO, US | 6 | 2005–2008 |
| Longmont, CO, US | 2 | 2010–2011 |
| Thornton, CO, US | 2 | 2008–2009 |