Inventor
Suresh Srinivas
Inventor
Portland, OR, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing89%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
PatentTitleYear
10,725,755Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads202010,120,663Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture20189,672,019'Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads'20179,542,191'Hardware profiling mechanism to enable page level automatic binary translation'20179,529,645'Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code'20169,417,855'Instruction and logic to perform dynamic binary translation'20169,189,233'Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads'20159,170,789'Analyzing potential benefits of vectorization'20158,972,994'Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment'20158,812,792'Technique for using memory attributes'20148,775,153'Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment'20148,762,127'Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment'20148,560,781'Technique for using memory attributes'20137,991,956'Providing application-level information for use in cache management'20117,991,965'Technique for using memory attributes'20117,415,701'Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2020Patents assigned to INTEL CORP (16)· patent assignee history
2008–2020Based in Portland, OR, US· patent location history
2013–2017Patents assigned to SRINIVAS SURESH (7)· patent assignee history
2014–2017Patents assigned to YAMADA KOICHI (4)· patent assignee history
2015–2017Patents assigned to BOBBA JAYARAM (2)· patent assignee history
2016–2017Patents assigned to CAPRIOLI PAUL (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 16 | 2008–2020 |
| SRINIVAS SURESHself | 7 | 2013–2017 |
| YAMADA KOICHI | 4 | 2014–2017 |
| BOBBA JAYARAM | 2 | 2015–2017 |
| CAPRIOLI PAUL | 2 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 16 | 2008–2020 |