Inventor
Naoyuki Shigyo
Inventor
Yokohama, JP
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10BElectronic memory devices15%
G11CStatic stores12%
G06FElectric digital data processing8%
G06TImage data processing or generation, in general4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
8,533,549'Memory system and computer system'20138,503,245'Non-volatile semiconductor memory device and a programming method thereof'20138,369,152'Semiconductor memory device including charge accumulation layer'20137,999,324'Semiconductor device including overcurrent protection element'20117,823,114'Method of designing wiring structure of semiconductor device and wiring structure designed accordingly'20107,373,627'Method of designing wiring structure of semiconductor device and wiring structure designed accordingly'20086,978,434'Method of designing wiring structure of semiconductor device and wiring structure designed accordingly'20056,956,747'Semiconductor device'20056,222,224'Erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory'20016,195,790'Electrical parameter evaluation system, electrical parameter evaluation method, and computer-readable recording medium for recording electrical parameter evaluation program'20016,051,452'Method for manufacturing a semiconductor device with ion implantation'20005,760,442'Semiconductor device of a silicon on insulator metal-insulator type with a concave feature'19985,698,869'Insulated-gate transistor having narrow-bandgap-source'19975,485,028'Semiconductor device having a single crystal semiconductor layer formed on an insulating film'19965,463,234'High-speed semiconductor gain memory cell with minimal area occupancy'19955,254,867'Semiconductor devices having an improved gate'19934,941,114'Triangular mesh generation method'19904,651,411'Method of manufacturing a MOS device wherein an insulating film is deposited in a field region'19874,636,824'Voltage-controlled type semiconductor switching device'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987Patents assigned to TOKYO SHIBAURA ELECTRIC CO (2)· patent assignee history
1987–2013Based in Yokohama, JP· patent location history
1990–2013Patents assigned to TOSHIBA KK (17)· patent assignee history
1995–2013Based in Kanagawa, JP· patent location history
1997–2001Based in Tokyo, JP· patent location history
2001Based in Tokoy, JP· patent location history
2013Patents assigned to SHIGYO NAOYUKI (3)· patent assignee history
2013Patents assigned to HOGYOKU MICHIRU (1)· patent assignee history
2013Patents assigned to HORII HIDETO (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 17 | 1990–2013 |
| SHIGYO NAOYUKIself | 3 | 2013 |
| TOKYO SHIBAURA ELECTRIC CO | 2 | 1987 |
| HOGYOKU MICHIRU | 1 | 2013 |
| HORII HIDETO | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yokohama, JP | 13 | 1987–2013 |
| Kanagawa, JP | 3 | 1995–2013 |
| Tokyo, JP | 2 | 1997–2001 |
| Tokoy, JP | 1 | 2001 |