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Inventor

Dirk Leipold

Inventor
Plano, TX, US

Overview

57→
Patents
2001–2018
Patent span
Electricity
Primary field (CPC H)

Patents· 57 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses23%
H04BTransmission17%
H04LTransmission of digital information, e.g. telegraphic communication16%
H03KPulse technique11%
H03FAmplifiers8%
H03CModulation7%
H03DDemodulation or transference of modulation from one carrier to another5%
G01RMeasuring electric variables2%
H03HImpedance networks, e.g. resonant circuits2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
9,893,735'Digital phase locked loop'20189,680,487'RF circuit, DCO, frequency divider with three divided clock outputs'20179,294,108'RF circuit with DCO, state machine, latch, modulator, timing update'20169,094,184'First and second phase detectors and phase offset adder PLL'20158,855,236'Digital amplitude modulation'20148,742,808'Digital phase locked loop'20148,559,579'All-digital frequency synthesis with DCO gain calculation'20138,542,616'Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing'20138,411,793'Digital amplitude modulation'20138,385,476'Digital phase locked loop'20138,306,176'Fine-grained gear-shifting of a digital phase-locked loop (PLL)'20128,284,886'Radio frequency built-in self test for quality monitoring of local oscillator and transmitter'20128,155,256'Method and apparatus for asynchronous clock retiming'20128,027,657'Sampling mixer with asynchronous clock and signal domains'20118,017,935'Parallel redundant single-electron device and method of manufacture'20118,000,670'Removing close-in interferers through a feedback loop'20118,000,428'All-digital frequency synthesis with DCO gain calculation'20117,958,408'On-chip receiver sensitivity test mechanism'20117,929,637'Method and apparatus for digital amplitude and phase modulation'20117,834,686'Power amplifier'20107,813,462'Method of defining semiconductor fabrication process utilizing transistor inverter delay period'20107,791,407'Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing'20107,767,995'Single-electron tunnel junction for complementary metal-oxide device and method of manufacturing the same'20107,667,511'Efficient pulse amplitude modulation transmit modulation'20107,623,838'Sampling mixer with asynchronous clock and signal domains'20097,575,969'Buried layer and method'20097,567,138'Single-electron injection/extraction device for a resonant tank circuit and method of operation thereof'20097,555,057'Predistortion calibration in a transceiver assembly'20097,519,135'Direct radio frequency (RF) sampling with recursive filtering method'20097,483,508'All-digital frequency synthesis with non-linear differential term for handling frequency perturbations'20097,466,207'Gain calibration of a digital controlled oscillator'20087,463,873'Wireless communications device having type-II all-digital phase-locked loop (PLL)'20087,463,869'Low noise high isolation transmit buffer gain control mechanism'20087,440,511'Transmit filter'20087,427,940'Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, SOC including such converter and method of phase detection for use in synthesizing a clock signal'20087,411,444'Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing'20087,405,685'Negative contributive offset compensation in a transmit buffer utilizing inverse clocking'20087,382,200'Type-II all-digital phase-locked loop (PLL)'20087,254,755'On-chip receiver sensitivity test mechanism'20077,218,904'Removing close-in interferers through a feedback loop'20077,183,860'Gain calibration of a digital controlled oscillator'20077,145,399'Type-II all-digital phase-locked loop (PLL)'20067,057,540'Sigma-delta (ΣΔ) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer'20067,035,750'On-chip test mechanism for transceiver power amplifier and oscillator frequency'20067,006,813'Efficient charge transfer using a switched capacitor resistor'20066,959,049'Multi-tap, digital-pulse-driven mixer'20056,924,681'Efficient pulse amplitude modulation transmit modulation'20056,882,829'Integrated circuit incorporating RF antenna switch and power amplifier'20056,809,598'Hybrid of predictive and closed-loop phase-domain digital PLL architecture'20046,791,422'Frequency synthesizer with digitally-controlled oscillator'20046,734,741'Frequency synthesizer with digitally-controlled oscillator'20046,658,748'Digitally-controlled L-C oscillator'20036,606,004'System and method for time dithering a digitally-controlled oscillator tuning input'20036,593,773'Power saving circuitry using predictive logic'20036,429,693'Digital fractional phase detector'20026,414,555'Frequency synthesizer'20026,326,851'Digital phase-domain PLL frequency synthesizer'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2018Patents assigned to TEXAS INSTRUMENTS INC (57)· patent assignee history
2001–2014Based in Plano, TX, US· patent location history
2008Based in Dallas, TX, US· patent location history
2009–2013Based in Igis, CH· patent location history
2009Based in Obserschan, CH· patent location history
2012–2014Patents assigned to STASZEWSKI ROBERT B (8)· patent assignee history
2012–2014Patents assigned to LEIPOLD DIRK (7)· patent assignee history
2012–2013Patents assigned to MUHAMMAD KHURRAM (2)· patent assignee history
2013–2014Patents assigned to REZEQ SAMEH (2)· patent assignee history
2014–2018Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC572001–2018
STASZEWSKI ROBERT B82012–2014
LEIPOLD DIRKself72012–2014
MUHAMMAD KHURRAM22012–2013
REZEQ SAMEH22013–2014
Locations
LocationPatentsSpan
Plano, Texas, US452001–2014
San Jose, California, US52014–2018
Igis, CH52009–2013
Obserschan, CH12009
Dallas, Texas, US12008