Inventor
Yuan-Hung Chiu
Inventor
Taipei, TW
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1033%
H10DInorganic electric semiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H01LSemiconductor devices11%
H10BElectronic memory devices3%
H01JElectric discharge tubes or discharge lamps2%
B82YSpecific uses or applications of nanostructures1%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy1%
PatentTitleYear
11,127,631Semiconductor device with contact structures202111,121,138Low resistance pickup cells for SRAM202111,101,491Semiconductor structures having a micro-battery and methods for making the same202111,081,403Methods of forming contact features in field-effect transistors202111,063,041Integrated circuit device including a power supply line and method of forming the same202110,861,960FinFET device and method202010,825,907Self-aligned contact and manufacturing method thereof202010,164,032Self-aligned contact and manufacturing method thereof201810,032,887Method of forming a contact20189,627,258'Method of forming a contact'20179,349,831'Integrated circuit device with well controlled surface proximity and method of manufacturing same'20168,900,960'Integrated circuit device with well controlled surface proximity and method of manufacturing same'20148,614,132'Integrated circuit device with well controlled surface proximity and method of manufacturing same'20138,236,659'Source and drain feature profile for improving device performance and method of manufacturing same'20127,678,655'Spacer layer etch method providing enhanced microelectronic device performance'20107,510,940'Method for fabricating dual-gate semiconductor device'20097,446,050'Etching and plasma treatment process to improve a gate profile'20087,390,753'In-situ plasma treatment of advanced resists in fine pattern definition'20087,307,009'Phosphoric acid free process for polysilicon gate definition'20077,301,645'In-situ critical dimension measurement'20077,195,969'Strained channel CMOS device with fully silicided gate electrode'20077,109,085'Etching process to avoid polysilicon notching'20067,078,351'Photoresist intensive patterning and processing'20067,074,727'Process for improving dielectric properties in low-k organosilicate dielectric material'20067,060,628'Method for fabricating a hard mask polysilicon gate'20067,012,027'Zirconium oxide and hafnium oxide etching using halogen containing chemicals'20067,008,878'Plasma treatment and etching process for ultra-thin dielectric films'20066,900,104'Method of forming offset spacer manufacturing for critical dimension precision'20056,884,736'Method of forming contact plug on silicide structure'20056,869,868'Method of fabricating a MOSFET device with metal containing gate structures'20056,867,084'Gate structure and method of forming the gate dielectric with mini-spacer'20056,849,531'Phosphoric acid free process for polysilicon gate definition'20056,828,237'Sidewall polymer deposition method for forming a patterned microelectronic layer'20046,828,198'System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process'20046,818,553'Etching process for high-k gate dielectrics'20046,812,044'Advanced control for plasma process'20046,777,340'Method of etching a silicon containing layer using multilayer masks'20046,764,903'Dual hard mask layer patterning method'20046,524,938'Method for gate formation with improved spacer profile control'20036,503,848'Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window'20036,407,002'Partial resist free approach in contact etch to improve W-filling'20026,333,271'Multi-step plasma etch method for plasma etch processing a microelectronic layer'20016,297,162'Method to reduce silicon oxynitride etch rate in a silicon oxide dry etch'20016,235,653'Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (34)· patent assignee history
2001–2020Based in Taipei, TW· patent location history
2006Based in Hsinchu, TW· patent location history
2012–2013Patents assigned to CHEN YEN-MING (2)· patent assignee history
2012–2013Patents assigned to CHENG CHUN-FAI (2)· patent assignee history
2012–2013Patents assigned to CHIU YUAN-HUNG (2)· patent assignee history
2017–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (10)· patent assignee history
2021Based in Hsinchu County, TW· patent location history
2021Based in Zhubei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 34 | 2001–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 10 | 2017–2021 |
| CHEN YEN-MING | 2 | 2012–2013 |
| CHENG CHUN-FAI | 2 | 2012–2013 |
| CHIU YUAN-HUNGself | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 38 | 2001–2020 |
| Hsinchu County, TW | 4 | 2021 |
| Zhubei, TW | 1 | 2021 |
| Hsinchu, TW | 1 | 2006 |