Inventor

Scott Robins

Inventor

San Jose, CA, US

Overview

2002–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices42%

G11CStatic stores19%

H10BElectronic memory devices19%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

H01LSemiconductor devices4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

10,886,273Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors2021 10,373,956Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors2019 9,691,465'Thyristors, methods of programming thyristors, and methods of forming thyristors'2017 9,361,966'Thyristors'2016 8,952,418'Gated bipolar junction transistors'2015 8,519,431'Thyristors'2013 8,093,107'Thyristor semiconductor memory and method of manufacture'2012 8,017,998'Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure'2011 7,968,381'Fin thyristor-based semiconductor device'2011 7,894,256'Thyristor based memory cell'2011 7,894,255'Thyristor based memory cell'2011 7,858,449'Thyristor device with carbon lifetime adjustment implant and its method of fabrication'2010 7,859,011'High ion/Ioff SOI MOSFET using body voltage control'2010 7,554,130'Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region'2009 7,491,586'Semiconductor device with leakage implant and method of fabrication'2009 7,489,008'High Ion/Ioff SOI MOSFET using body voltage control'2009 7,488,626'Thyristor device with carbon lifetime adjustment implant and its method of fabrication'2009 7,374,974'Thyristor-based device with trench dielectric material'2008 7,320,895'Thyristor-based device having dual control ports'2008 7,245,525'Data restore in thryistor based memory devices'2007 7,183,591'Trench isolation for thyristor-based device'2007 7,157,342'Thyristor-based semiconductor memory device and its method of manufacture'2007 7,135,745'Fin thyristor-based semiconductor device'2006 7,125,753'Self-aligned thin capacitively-coupled thyristor structure'2006 7,109,532'High Ion/Ioff SOI MOSFET using body voltage control'2006 7,075,122'Thyristor device with carbon lifetime adjustment implant and its method of fabrication'2006 7,064,977'Reference cells for TCCT based memory cells'2006 7,054,191'Method and system for writing data to memory cells'2006 7,053,423'Thyristor having a first emitter with relatively lightly doped portion to the base'2006 7,049,182'Shunt connection to the emitter of a thyristor'2006 7,037,763'Gated-thyristor approach having angle-implanted base region'2006 7,030,425'Buried emitter contact for thyristor-based semiconductor device'2006 7,015,077'Varied trench depth for thyristor isolation'2006 6,998,652'Trench isolation for thyristor-based device'2006 6,980,457'Thyristor-based device having a reduced-resistance contact to a buried emitter region'2005 6,979,602'Method for making a recessed thyristor control port'2005 6,965,129'Thyristor-based device having dual control ports'2005 6,944,051'Data restore in thryistor based memory devices'2005 6,940,772'Reference cells for TCCT based memory cells'2005 6,913,955'Method of manufacturing a thyristor device with a control port in a trench'2005 6,911,680'Self-aligned thin capacitively-coupled thyristor structure'2005 6,901,021'Reference cells for TCCT based memory cells'2005 6,891,205'Stability in thyristor-based memory device'2005 6,888,177'Increased base-emitter capacitance'2005 6,872,602'Carrier coupler for thyristor-based semiconductor device'2005 6,835,997'Thyristor-based device with trench dielectric material'2004 6,828,176'Thyristor having a first emitter with relatively lightly doped portion to the base'2004 6,818,482'Method for trench isolation for thyristor-based device'2004 6,815,734'Varied trench depth for thyristor isolation'2004 6,777,271'Thyristor-based device including trench isolation'2004 6,767,770'Method of forming self-aligned thin capacitively-coupled thyristor structure'2004 6,756,612'Carrier coupler for thyristor-based semiconductor device'2004 6,727,528'Thyristor-based device including trench dielectric isolation for thyristor-body regions'2004 6,703,646'Thyristor with lightly-doped emitter'2004 6,690,039'Thyristor-based device that inhibits undesirable conductive channel formation'2004 6,690,038'Thyristor-based device over substrate surface'2004 6,686,612'Thyristor-based device adapted to inhibit parasitic current'2004 6,683,330'Recessed thyristor control port'2004 6,666,481'Shunt connection to emitter'2003 6,653,175'Stability in thyristor-based memory device'2003 6,653,174'Thyristor-based device over substrate surface'2003 6,583,452'Thyristor-based device having extended capacitive coupling'2003 6,462,359'Stability in thyristor-based memory device'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2006Patents assigned to T RAM INC (36)· patent assignee history

2002–2021Based in San Jose, CA, US· patent location history

2006–2012Patents assigned to T RAM SEMICONDUCTOR INC (19)· patent assignee history

2006–2015Patents assigned to NEMATI FARID (4)· patent assignee history

2013–2021Patents assigned to MICRON TECHNOLOGY INC (6)· patent assignee history

2013–2015Patents assigned to GUPTA RAJESH N (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
T RAM INC	36	2002–2006
T RAM SEMICONDUCTOR INC	19	2006–2012
MICRON TECHNOLOGY INC	6	2013–2021
NEMATI FARID	4	2006–2015
GUPTA RAJESH N	2	2013–2015

Locations

Location	Patents	Span
San Jose, California, US	63	2002–2021