Inventor
Nobuyuki Moriwaki
Inventor
Kyoto, JP
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores37%
H10BElectronic memory devices19%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests18%
H10DInorganic electric semiconductor devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G01RMeasuring electric variables1%
PatentTitleYear
7,844,874'Semiconductor integrated circuit device and inspection method therefor'20106,927,594'Evaluation device for evaluating semiconductor device'20056,067,265'Reference potential generator and a semiconductor memory device having the same'20006,038,160'Ferroelectric semiconductor memory device'20005,953,277'Reference potential generator and a semiconductor memory device having the same'19995,898,608'Method for operating a ferroelectric memory'19995,834,851'SRAM having load transistor formed above driver transistor'19985,828,615'Reference potential generator and a semiconductor memory device having the same'19985,767,554'Semiconductor integrated circuit device and process for fabricating the same'19985,751,628'Ferroelectric memory devices and method for testing them'19985,731,219'Process for fabricating a semiconductor integrated circuit device'19985,700,704'Process for fabricating a semiconductor integrated circuit device'19975,675,530'Ferroelectric memory device'19975,656,836'Semiconductor integrated circuit device and process for fabricating the same'19975,652,457'Semiconductor integrated circuit device and process for fabricating the same'19975,572,480'Semiconductor integrated circuit device and process for fabricating the same'19965,546,342'Semiconductor memory device including reverse and rewrite means'19965,523,974'Semiconductor memory device with redundant memory cell backup'19965,515,312'Semiconductor memory device'19965,467,302'Semiconductor memory device'19955,396,100'Semiconductor integrated circuit device having a compact arrangement of SRAM cells'19955,392,234'Semiconductor memory device'19955,239,196'SRAM with dual word lines overlapping drive transistor gates'19935,146,427'High speed semiconductor memory having a direct-bypass signal path'19925,132,771'Semiconductor memory device having flip-flop circuits'19925,025,422'Semiconductor memory device'19914,853,894'Static random-access memory having multilevel conductive layer'19894,841,486'Semiconductor memory device and sense amplifier'19894,797,717'Semiconductor memory device'19894,747,082'Semiconductor memory with automatic refresh means'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–1998Patents assigned to HITACHI LTD (15)· patent assignee history
1988–1995Patents assigned to HITACHI VLSI ENG (4)· patent assignee history
1988–1992Based in Kodaira, JP· patent location history
1993Patents assigned to HASHIBA SOICHIRO (1)· patent assignee history
1993Based in Ukyo-Ku, JP· patent location history
1995–2005Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (11)· patent assignee history
1995–2010Based in Kyoto, JP· patent location history
1998–2000Patents assigned to MATSUSHITA ELECTRONICS CORP (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 15 | 1988–1998 |
| MATSUSHITA ELECTRIC INDUSTRIAL CO LTD | 11 | 1995–2005 |
| HITACHI VLSI ENG | 4 | 1988–1995 |
| MATSUSHITA ELECTRONICS CORP | 2 | 1998–2000 |
| HASHIBA SOICHIRO | 1 | 1993 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kyoto, JP | 22 | 1995–2010 |
| Kodaira, JP | 7 | 1988–1992 |
| Ukyo-Ku, JP | 1 | 1993 |