Inventor
Harshavardhan Kaushikkar
Inventor
San Jose, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing59%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%
H04LTransmission of digital information, e.g. telegraphic communication12%
H04WWireless communication networks6%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
G11CStatic stores3%
PatentTitleYear
11,030,102Reducing memory cache control command hops on a fabric202111,016,913Inter cluster snoop latency reduction202110,877,888Systems and methods for providing distributed global ordering202010,802,968Processor to memory with coherency bypass202010,795,818Method and apparatus for ensuring real-time snoop latency202010,678,691Coherence flows for dual-processing pipelines202010,642,740Methods for performing a memory resource retry202010,417,146Real-time resource handling in resource retry queue201910,298,511Communication queue management system201910,206,175Communications fabric with split paths for control and data packets201910,169,235Methods of overriding a resource retry20199,990,294Methods for performing a memory resource retry20189,860,841'Communications fabric with split paths for control and data packets'20189,524,261'Credit lookahead mechanism'20169,465,740'Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers'20169,454,482'Duplicate tag structure employing single-port tag RAM and dual-port state RAM'20169,317,102'Power control for cache structures'20169,280,471'Mechanism for sharing private caches in a SoC'20169,201,791'Flow-ID dependency checking logic'20159,158,691'Cross dependency checking logic'20159,021,306'Debug access mechanism for duplicate tag storage'20158,904,073'Coherence processing with error checking'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2021Patents assigned to APPLE INC (22)· patent assignee history
2014–2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLE INC | 22 | 2014–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 22 | 2014–2021 |