Inventor
Darwin A. Clampitt
Inventor
Boise, ID, US
Overview
Patents· 60 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices36%
H10DInorganic electric semiconductor devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
H01LSemiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G11CStatic stores3%
E04HBuildings or like structures for particular purposes1%
F16MFrames, casings or beds of engines, machines or apparatus, not specific to engines, machines or apparatus provided for elsewhere1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
11,121,146Forming terminations in stacked memory arrays202111,101,280Memory arrays and methods used in forming a memory array202111,094,592Semiconductor devices and systems comprising memory cells and a source202111,043,412Methods of forming microelectronic devices, and related microelectronic devices and electronic systems202110,923,494Electronic devices comprising a source below memory cells and related systems202110,658,380Formation of termination structures in stacked memory arrays202010,566,241Methods of forming a semiconductor device, and related semiconductor devices and systems20208,365,751'Multipurpose hunting blinds, methods of making hunting blinds and methods of using hunting blinds'20138,052,104'Mounting head'20117,709,877'High surface area capacitor structures and precursors'20107,560,799'Spacer patterned, high dielectric constant capacitor'20097,388,290'Spacer patterned, high dielectric constant capacitor and methods for fabricating the same'20086,933,552'High surface area capacitors and intermediate storage poly structures formed during fabrication thereof'20056,919,612'Biasable isolation regions using epitaxially grown silicon between the isolation regions'20056,815,754'Spacer patterned, high dielectric constant capacitor'20046,790,738'Buried digit spacer separated capacitor array'20046,756,283'Method of fabricating a high surface area capacitor electrode'20046,723,602'Method for spacer patterned, high dielectric constant capacitor'20046,716,719'Method of forming biasable isolation regions using epitaxially grown silicon between the isolation regions'20046,686,235'Buried digit spacer-separated capacitor array'20046,680,502'Buried digit spacer separated capacitor array'20046,649,467'Method of making high density semiconductor memory'20036,589,838'Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines'20036,566,702'Spacer patterned, high dielectric constant capacitor'20036,566,206'Semiconductor structure having more usable substrate area and method for forming same'20036,551,878'Mini flash process and circuit'20036,479,855'Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines'20026,458,654'Large surface area capacitor and methods for fabricating same'20026,455,367'Method of making high density semiconductor memory'20026,429,475'Cell capacitors, memory cells, memory arrays, and method of fabrication'20026,420,270'Method of producing an etch pattern'20026,413,831'Method of fabrication for a honeycomb capacitor'20026,413,855'Methods of making interconnections for semiconductor circuits'20026,414,351'Mini FLASH process and circuit'20026,403,430'Semiconductor structure having more usable substrate area and method for forming same'20026,373,123'Semiconductor structure having more usable substrate area and method for forming same'20026,352,932'Methods of forming integrated circuitry and integrated circuitry structures'20026,242,301'Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines'20016,225,159'Cell capacitors, memory cells, memory arrays, and method of fabrication'20016,204,114'Method of making high density semiconductor memory'20016,198,158'Memory circuit including a semiconductor structure having more usable substrate area'20016,191,444'Mini flash process and circuit'20016,190,965'Spacer patterned, high dielectric constant capacitor'20016,187,621'Semiconductor processing methods of forming capacitor constructions and semiconductor processing methods of forming DRAM constructions'20016,160,283'Methods of forming integrated circuitry and integrated circuitry structures'20006,153,903'Cell capacitors, memory cells, memory arrays, and method of fabrication'20006,150,691'Spacer patterned, high dielectric constant capacitor'20006,114,720'Capacitor and conductive line constructions'20006,103,565'Semiconductor processing methods of forming capacitors and conductive lines'20006,087,263'Methods of forming integrated circuitry and integrated circuitry structures'20006,081,033'Interconnections for semiconductor circuits'20006,066,539'Honeycomb capacitor and method of fabrication'20006,063,656'Cell capacitors, memory cells, memory arrays, and method of fabrication'20006,034,417'Semiconductor structure having more usable substrate area and method for forming same'20005,994,232'Etching method for use in fabrication semiconductor device'19995,939,741'Methods of forming integrated circuitry and integrated circuitry structures'19995,936,874'High density semiconductor memory and method of making'19995,932,928'Semiconductor circuit interconnections and methods of making such interconnections'19995,798,303'Etching method for use in fabrication of semiconductor devices'19985,773,341'Method of making capacitor and conductive line constructions'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2021Patents assigned to MICRON TECHNOLOGY INC (58)· patent assignee history
1998–2010Based in Boise, ID, US· patent location history
2004–2005Based in Homedale, ID, US· patent location history
2011–2013Patents assigned to INTUITIVE CORP (2)· patent assignee history
2011–2021Based in Wilder, ID, US· patent location history
2013Patents assigned to CLAMPITT DARWIN A (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 58 | 1998–2021 |
| INTUITIVE CORP | 2 | 2011–2013 |
| CLAMPITT DARWIN Aself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 46 | 1998–2010 |
| Wilder, ID, US | 9 | 2011–2021 |
| Homedale, ID, US | 5 | 2004–2005 |