Inventor

Alan S. Krech, Jr.

Inventor

Fort Collins, CO, US

Overview

1997–2021

Patent span

Physics

Primary field (CPC G)

Patents· 49 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Tprimary

G06TImage data processing or generation, in general26%

G11CStatic stores26%

G06FElectric digital data processing19%

G01RMeasuring electric variables17%

G09GArrangements or circuits for control of indicating devices using static means to present variable information3%

H03KPulse technique3%

H04BTransmission3%

H04LTransmission of digital information, e.g. telegraphic communication3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

10,948,540Integrated protocol analyzer configured within automated test equipment (ate) hardware2021 10,693,568Adapting serdes receivers to a UFS receiver protocol2020 10,652,131Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array2020 9,842,038'Method and system for advanced fail data transfer mechanisms'2017 9,612,272'Testing memory devices with parallel processing operations'2017 9,281,080'Staged buffer caching in a system for testing a device under test'2016 9,267,965'Flexible test site synchronization'2016 7,404,122'Mapping logic for loading control of crossbar multiplexer select RAM'2008 7,339,844'Memory device fail summary data reduction for improved redundancy analysis'2008 7,181,660'Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test'2007 7,076,714'Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors'2006 6,973,404'Method and apparatus for administering inversion property in a memory tester'2005 6,968,545'Method and apparatus for no-latency conditional branching'2005 6,834,364'Algorithmically programmable memory tester with breakpoint trigger, error jamming and \'scope mode that memorizes target sequences'2004 6,833,695'Simultaneous display of data gathered using multiple data gathering mechanisms'2004 6,781,584'Recapture of a portion of a displayed waveform without loss of existing data in the waveform display'2004 6,779,140'Algorithmically programmable memory tester with test sites operating in a slave mode'2004 6,763,490'Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester'2004 6,748,562'Memory tester omits programming of addresses in detected bad columns'2004 6,687,855'Apparatus and method for storing information during a test program'2004 6,671,844'Memory tester tests multiple DUT\'s per test site'2003 6,598,112'Method and apparatus for executing a program using primary, secondary and tertiary memories'2003 6,591,385'Method and apparatus for inserting programmable latency between address and data information in a memory tester'2003 6,574,764'Algorithmically programmable memory tester with history FIFO\'s that aid in error analysis and recovery'2003 6,574,626'Method and apparatus for administration of extended memory'2003 6,219,071'ROM-based control unit in a geometry accelerator for a computer graphics system'2001 6,184,902'Centralized branch intelligence system and method for a geometry accelerator'2001 6,057,852'Graphics accelerator with constant color identifier'2000 6,003,098'Graphic accelerator architecture using two graphics processing units for processing aspects of pre-rasterized graphics primitives and a control circuitry for relaying pass-through information'1999 5,969,726'Caching and coherency control of multiple geometry accelerators in a computer graphics system'1999 5,956,042'Graphics accelerator with improved lighting processor'1999 5,956,047'ROM-based control units in a geometry accelerator for a computer graphics system'1999 5,949,440'Method and apparatus for processing graphics primitives in multiple modes using reconfigurable hardware'1999 5,940,086'System and method for dynamically allocating data among geometry accelerators in a computer graphics system'1999 5,930,519'Distributed branch logic system and method for a geometry accelerator'1999 5,920,326'Caching and coherency control of multiple geometry accelerators in a computer graphics system'1999 5,912,830'System and method for conditionally calculating exponential values in a geometry accelerator'1999 5,886,711'Method and apparatus for processing primitives in a computer graphics display system'1999 5,883,641'System and method for speculative execution in a geometry accelerator'1999 5,831,991'Methods and apparatus for electrically verifying a functional unit contained within an integrated cirucuit'1998 5,821,950'Computer graphics system utilizing parallel processing for enhanced performance'1998 5,822,516'Enhanced test method for an application-specific memory scheme'1998 5,801,711'Polyline and triangle strip data management techniques for enhancing performance of computer graphics system'1998 5,796,288'Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor'1998 5,784,075'Memory mapping techniques for enhancing performance of computer graphics system'1998 5,767,859'Method and apparatus for clipping non-planar polygons'1998 5,696,944'Computer graphics system having double buffered vertex ram with granularity'1997 5,664,114'Asynchronous FIFO queuing system operating with minimal queue status'1997 5,657,443'Enhanced test system for an application-specific memory scheme'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2001Patents assigned to HEWLETT PACKARD CO (22)· patent assignee history

1997–2020Based in Fort Collins, CO, US· patent location history

1999Patents assigned to HEWLETT PACKARD COMPANU (1)· patent assignee history

1999Patents assigned to HEWLETT PACKARD COMPNAY (1)· patent assignee history

2003–2008Patents assigned to AGILENT TECHNOLOGIES INC (16)· patent assignee history

2016–2021Patents assigned to ADVANTEST CORP (7)· patent assignee history

2020–2021Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HEWLETT PACKARD CO	22	1997–2001
AGILENT TECHNOLOGIES INC	16	2003–2008
ADVANTEST CORP	7	2016–2021
HEWLETT PACKARD COMPANU	1	1999
HEWLETT PACKARD COMPNAY	1	1999

Locations

Location	Patents	Span
Fort Collins, CO, US	47	1997–2020
San Jose, California, US	2	2020–2021