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Inventor

Saurabh Lodha

Inventor
Maharashtra, IN

Overview

2→
Patents
2011–2018
Patent span
Electricity
Primary field (CPC H)

Patents· 2 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
C23FNon-mechanical removal of metallic material from surface14%
H01LSemiconductor devices14%
H10DInorganic electric semiconductor devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
Y10TTechnical subjects covered by former us classification14%
PatentTitleYear
10,043,684Self-limiting atomic thermal etching systems and methods20187,861,406'Method of forming CMOS transistors with dual-metal silicide formed through the contact openings'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2011Patents assigned to INTEL CORP (1)· patent assignee history
2011Based in Hillsboro, OR, US· patent location history
2018Patents assigned to APPLIED MATERIALS INC (1)· patent assignee history
2018Based in Maharashtra, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
APPLIED MATERIALS INC12018
INTEL CORP12011
Locations
LocationPatentsSpan
Maharashtra, IN12018
Hillsboro, OR, US12011