Inventor
Bai-Sun Kong
Inventor
Seoul, KR
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique39%
G11CStatic stores22%
G06FElectric digital data processing15%
H04NPictorial communication, e.g. television7%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems4%
H03MCoding4%
H03FAmplifiers2%
H03HImpedance networks, e.g. resonant circuits2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,243,567Flip-flop and driving method thereof201910,148,283Delta-sigma modulator20189,742,428'Delta sigma modulator for shaping noise and audio codec having the same'20179,276,574'Scan flip-flop circuits and scan test circuits including the same'20169,214,925'Clock gated circuit and digital system having the same'20158,907,701'CMOS differential logic circuit using voltage boosting technique'20148,441,279'Scan flip-flop circuits and scan test circuits including the same'20138,130,028'CMOS charge pump with improved latch-up immunity'20128,004,311'Input/output circuit and integrated circuit apparatus including the same'20117,928,795'Semiconductor device for charge pumping'20117,928,792'Apparatus for outputting complementary signals using bootstrapping technology'20117,724,073'Charge pump circuit'20107,724,605'Clock-based data storage device, dual pulse generation device, and data storage device'20107,528,630'High speed flip-flop'20097,504,871'Flip-flops and electronic digital circuits including the same'20097,446,607'Regulated cascode circuit, an amplifier including the same, and method of regulating a cascode circuit'20086,717,448'Data output method and data output circuit for applying reduced precharge level'20046,242,973'Bootstrapped CMOS driver'20016,211,704'Asynchronous sensing differential logic (ASDL) circuit'20016,163,193'Self-timed latch circuit for high-speed very large scale integration (VLSI)'20006,028,453'Charge recycling differential logic (CRDL) circuit having true single-phase clocking scheme'20006,016,065'Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same'20005,903,169'Charge recycling differential logic (CRDL) circuit and storage elements and devices using the same'19995,859,548'Charge recycling differential logic (CRDL) circuit and devices using the same'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2000Patents assigned to LG SEMICON CO LTD (4)· patent assignee history
1999–2019Based in Seoul, KR· patent location history
1999Based in Nowon-gu, KR· patent location history
2000–2001Patents assigned to HYUNDAI ELECTRONICS IND (3)· patent assignee history
2004–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (12)· patent assignee history
2009–2017Based in Suwon-si, KR· patent location history
2009Based in Hwaseong-si, KR· patent location history
2010–2015Patents assigned to UNIV SUNGKYUNKWAN FOUND (3)· patent assignee history
2010Based in Gyeonggi-do, KR· patent location history
2012–2015Patents assigned to KONG BAI-SUN (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 12 | 2004–2017 |
| LG SEMICON CO LTD | 4 | 1999–2000 |
| HYUNDAI ELECTRONICS IND | 3 | 2000–2001 |
| KONG BAI-SUNself | 3 | 2012–2015 |
| UNIV SUNGKYUNKWAN FOUND | 3 | 2010–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seoul, KR | 12 | 1999–2019 |
| Suwon-si, KR | 9 | 2009–2017 |
| Gyeonggi-do, KR | 1 | 2010 |
| Hwaseong-si, KR | 1 | 2009 |
| Nowon-gu, KR | 1 | 1999 |