Inventor
Toshinori Koyama
Inventor
Nagano, JP
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits32%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H01LSemiconductor devices12%
Y02PClimate change mitigation technologies in the production or processing of goods7%
Y10TTechnical subjects covered by former us classification7%
A45DHairdressing or shaving equipment5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
C23FNon-mechanical removal of metallic material from surface2%
G02BOptical elements, systems or apparatus2%
G03BApparatus or arrangements for taking photographs or for projecting or viewing them2%
PatentTitleYear
9,820,391'Wiring board'20179,620,446'Wiring board, electronic component device, and method for manufacturing those'20179,520,352'Wiring board and semiconductor device'20169,455,219'Wiring substrate and method of manufacturing the same'20169,380,707'Method of manufacturing wiring substrate'20169,220,167'Wiring substrate, semiconductor device, and method of manufacturing wiring substrate'20159,167,692'Wiring board, semiconductor device, and method of manufacturing wiring board'20157,964,950'Electronic parts packaging structure and method of manufacturing the same'20117,691,673'Electronic parts packaging structure and method of manufacturing the same'20107,573,135'Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film'20097,545,049'Electronic parts packaging structure'20097,498,200'Electronic-parts-packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film'20097,495,745'Patterning method and computer readable medium therefor'20097,307,691'Maskless direct exposure system and user interface'20077,285,862'Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film'20077,057,290'Electronic parts packaging structure and method of manufacturing the same'20066,759,600'Multilayer wiring board and method of fabrication thereof'20046,560,863'Method of producing wiring board'20036,350,365'Method of producing multilayer circuit board'20026,254,758'Method of forming conductor pattern on wiring board'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2017Patents assigned to SHINKO ELECTRIC IND CO (20)· patent assignee history
2001–2017Based in Nagano, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SHINKO ELECTRIC IND CO | 20 | 2001–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nagano, JP | 20 | 2001–2017 |