Inventor
George A. Spix
Inventor
Eau Claire, WI, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing96%
H04LTransmission of digital information, e.g. telegraphic communication4%
PatentTitleYear
6,195,676'Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes'20015,745,721'Partitioned addressing apparatus for vector/scalar registers'19985,717,881'Data processing system for processing one and two parcel instructions'19985,706,490'Method of processing conditional branch instructions in scalar/vector processor'19985,659,706'Vector/scalar processor with simultaneous processing and instruction cache filling'19975,640,524'Method and apparatus for chaining vector instructions'19975,623,650'Method of processing a sequence of conditional vector IF statements'19975,598,547'Vector processor having functional unit paths of differing pipeline lengths'19975,561,784'Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses'19965,544,337'Vector processor having registers for control by vector resisters'19965,524,255'Method and apparatus for accessing global registers in a multiprocessor system'19965,499,356'Method and apparatus for a multiprocessor resource lockout instruction'19965,452,452'System having integrated dispatcher for self scheduling processors to execute multiple types of processes'19955,430,884'Scalar/vector processor'19955,428,803'Method and apparatus for a unified parallel processing architecture'19955,388,217'Distributing system for multi-processor input and output using channel adapters'19955,339,415'Dual level scheduling of processes to multiple parallel regions of a multi-threaded program on a tightly coupled multiprocessor computer system'19945,253,359'Control and maintenance subsystem network for use with a multiprocessor computer system'19935,239,629'Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system'19935,202,988'System for communicating among processors having different speeds'19935,197,130'Cluster architecture for a highly parallel scalar/vector multiprocessor system'19935,193,187'Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers'19935,179,702'System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling'19935,168,547'Distributed architecture for input/output for a multiprocessor system'19925,165,038'Global registers for a multiprocessor system'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–1993Patents assigned to SUPERCOMPUTER SYSTEMS LTD (8)· patent assignee history
1992–2001Based in Eau Claire, WI, US· patent location history
1994–1998Patents assigned to CRAY RESEARCH INC (16)· patent assignee history
2001Patents assigned to SILICON GRAPHICS INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CRAY RESEARCH INC | 16 | 1994–1998 |
| SUPERCOMPUTER SYSTEMS LTD | 8 | 1992–1993 |
| SILICON GRAPHICS INC | 1 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Eau Claire, WI, US | 25 | 1992–2001 |