LexDanaLexDanabeta
Inventor

Vijay Karamcheti

Inventor
Los Altos, CA, US

Overview

97→
Patents
2010–2020
Patent span
Physics
Primary field (CPC G)

Patents· 97 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing53%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use24%
G11CStatic stores13%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
10,691,531Systems and methods for multi-zone data tiering for endurance extension in solid state drives202010,565,057Indirection-based storage system backups using markers including sets of serial numbers associated with segments202010,474,397Unified indirection in a multi-device hybrid storage unit201910,467,100High availability state machine and recovery201910,353,813Checkpoint based technique for bootstrapping forward map under constrained memory for flash devices201910,275,376Efficient cross device redundancy implementation on high performance direct attached non-volatile storage with data reduction201910,191,842Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory201910,156,890Network computer systems with power management201810,152,389Apparatus and method for inline compression and deduplication201810,089,360Apparatus and method for single pass entropy detection on data transfer201810,082,957Dual-ported PCI express-based storage cartridge including single-ported storage controllers201810,073,626Managing the write performance of an asymmetric memory system201810,049,055Managing asymmetric memory system as a cache device20189,983,797Memory server with read writeable non-volatile memory20189,984,012Read writeable randomly accessible non-volatile memory modules20189,898,196'Small block write operations in non-volatile memory systems'20189,842,660'System and method to improve enterprise reliability through tracking I/O performance metrics in non-volatile random access memory'20179,836,409Seamless application access to hybrid main memory20179,811,285'Dynamic restriping in nonvolatile memory systems'20179,767,867'Methods of communicating to different types of memory modules in a memory channel'20179,734,027'Synchronous mirroring in non-volatile memory systems'20179,733,840'Managing the write performance of an asymmetric memory system'20179,727,112'Methods for early write termination with non-volatile memory'20179,727,452'Distributing metadata across multiple different disruption regions within an asymmetric memory system'20179,678,665'Methods and systems for memory page allocation'20179,672,158'Asymmetric memory migration in hybrid main memory'20179,626,290'Memory channel connected non-volatile memory'20179,588,698'Managing the write performance of an asymmetric memory system'20179,552,384'Apparatus and method for single pass entropy detection on data transfer'20179,536,609'Memory modules with multi-chip packaged integrated circuits having flash memory'20179,513,695'Methods of managing power in network computer systems'20169,514,038'Managing memory systems containing components with asymmetric characteristics'20169,477,595'Managing the write performance of an asymmetric memory system'20169,436,597'Using non-volatile memory resources to enable a virtual buffer pool for a database application'20169,323,663'Managing the write performance of an asymmetric memory system'20169,304,908'Small block write operations in non-volatile memory systems'20169,286,002'Dynamic restriping in nonvolatile memory systems'20169,262,333'Asymmetric memory migration in hybrid main memory'20169,262,334'Seamless application access to hybrid main memory'20169,251,061'Methods for accessing memory in a two-dimensional main memory having a plurality of memory slices'20169,251,899'Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers'20169,223,719'Integrating data from symmetric and asymmetric memory'20159,213,637'Read and write performance for non-volatile memory'20159,164,891'Managing the write performance of an asymmetric memory system'20159,135,164'Synchronous mirroring in non-volatile memory systems'20159,122,588'Managing asymmetric memory system as a cache device'20159,093,150'Multi-chip packaged integrated circuit with flash memory and slave memory controller'20159,021,188'Small block write operations in non-volatile memory systems'20158,996,796'Small block write operations in non-volatile memory systems'20158,972,633'Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory'20158,949,555'Methods for sustained read and write performance with non-volatile memory'20158,943,245'Non-volatile type memory modules for main memory'20158,874,843'Systems with programmable heterogeneous memory controllers for main memory'20148,856,464'Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices'20148,850,091'Methods for early write termination with non-volatile memory'20148,806,116'Memory modules for two-dimensional main memory'20148,782,373'Seamless application access to hybrid main memory'20148,745,314'Methods for a random read and read/write block accessible memory'20148,706,932'Replaceable non-volatile memory apparatus with a plurality of pluggable electrical connectors'20148,689,042'Methods for data redundancy across replaceable non-volatile memory storage devices'20148,677,037'Memory apparatus for early write termination and power failure'20148,650,343'Methods for upgrading, diagnosing, and maintaining replaceable non-volatile memory'20148,639,910'Handling writes to a memory including asymmetric and symmetric components'20148,639,901'Managing memory systems containing components with asymmetric characteristics'20148,639,863'Memory apparatus for replaceable non-volatile memory'20148,555,024'Integrating data from symmetric and asymmetric memory'20138,555,002'Asymmetric memory migration in hybrid main memory'20138,521,967'Network computing systems having shared memory clouds with addresses of disk-read-only memories mapped into processor address spaces'20138,516,172'Methods for early write termination and power failure with non-volatile memory'20138,478,931'Using non-volatile memory resources to enable a virtual buffer pool for a database application'20138,463,993'Translating memory modules for main memory'20138,429,318'Methods for early write termination into non-volatile memory with metadata write operations'20138,417,873'Random read and read/write block accessible memory'20138,407,439'Managing memory systems containing components with asymmetric characteristics'20138,380,898'Methods for main memory with non-volatile type memory modules'20138,370,547'System and apparatus with a memory controller configured to control access to randomly accessible non-volatile memory'20138,370,548'Methods of assembly of a computer system with randomly accessible non-volatile memory'20138,364,867'Systems and apparatus for main memory'20138,341,300'Systems for sustained read and write performance with non-volatile memory'20128,266,407'Writing to asymmetric memory'20128,225,006'Methods for data redundancy across three or more storage devices'20128,205,061'Seamless application access to hybrid main memory'20128,200,932'Managing memory systems containing components with asymmetric characteristics'20128,176,233'Using non-volatile memory resources to enable a virtual buffer pool for a database application'20128,156,302'Integrating data from symmetric and asymmetric memory'20128,156,288'Asymmetric memory migration in hybrid main memory'20128,156,299'Managing memory systems containing components with asymmetric characteristics'20128,074,022'Programmable heterogeneous memory controllers for main memory with different memory modules'20118,051,253'Systems and apparatus with programmable memory control for heterogeneous main memory'20117,930,513'Writing to asymmetric memory'20117,913,055'Seamless application access to hybrid main memory'20117,818,489'Integrating data from symmetric and asymmetric memory'20107,774,556'Asymmetric memory migration in hybrid main memory'20107,761,625'Methods for main memory with non-volatile type memory modules, and related technologies'20107,761,623'Main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies'20107,761,626'Methods for main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies'20107,761,624'Systems and apparatus for main memory with non-volatile type memory modules, and related technologies'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2018Patents assigned to VIRIDENT SYSTEMS INC (78)· patent assignee history
2010–2019Based in Los Altos, CA, US· patent location history
2011–2017Patents assigned to KARAMCHETI VIJAY (42)· patent assignee history
2011–2016Patents assigned to GANAPATHY KUMAR (24)· patent assignee history
2011–2015Patents assigned to PAREKH RAJESH (16)· patent assignee history
2012–2014Patents assigned to OKIN KENNETH A (19)· patent assignee history
2012–2020Based in Palo Alto, CA, US· patent location history
2019–2020Based in Los Altos Hills, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
VIRIDENT SYSTEMS INC782010–2018
KARAMCHETI VIJAYself422011–2017
GANAPATHY KUMAR242011–2016
OKIN KENNETH A192012–2014
PAREKH RAJESH162011–2015
Locations
LocationPatentsSpan
Los Altos, California, US642010–2019
Palo Alto, California, US312012–2020
Los Altos Hills, California, US22019–2020