Inventor

Thomas G. Sopchak

Inventor
Williston, VT, US

Overview

19→
Patents
1998–2019
Patent span
Physics
Primary field (CPC G)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary
G01RMeasuring electric variables45%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
G06FElectric digital data processing13%
G11CStatic stores13%
H01LSemiconductor devices3%
PatentTitleYear
10,295,592Pre-test power-optimized bin reassignment following selective voltage binning20199,759,767'Pre-test power-optimized bin reassignment following selective voltage binning'20179,653,330'Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning'20177,620,931'Method of adding fabrication monitors to integrated circuit chips'20097,453,973'Diagnostic method and apparatus for non-destructively observing latch data'20087,323,278'Method of adding fabrication monitors to integrated circuit chips'20087,285,860'Method and structure for defect monitoring of semiconductor devices using power bus wiring grids'20077,239,167'Utilizing clock shield as defect monitor'20077,240,322'Method of adding fabrication monitors to integrated circuit chips'20077,194,706'Designing scan chains with specific parameter sensitivities to identify process defects'20077,145,977'Diagnostic method and apparatus for non-destructively observing latch data'20067,088,124'Utilizing clock shield as defect monitor'20067,089,514'Defect diagnosis for semiconductor integrated circuits'20067,078,248'Method and structure for defect monitoring of semiconductor devices using power bus wiring grids'20067,005,874'Utilizing clock shield as defect monitor'20067,007,214'Diagnosable scan chain'20066,998,866'Circuit and method for monitoring defects'20065,925,143'Scan-bypass architecture without additional external latches'19995,719,879'Scan-bypass architecture without additional external latches'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2009Patents assigned to IBM (16)· patent assignee history
1998–1999Based in Cambridge, VT, US· patent location history
2006–2019Based in Williston, VT, US· patent location history
2017–2019Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2019Patents assigned to GLOBAL FOUNDRIES INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM161998–2009
GLOBALFOUNDRIES INC32017–2019
GLOBAL FOUNDRIES INC12019
Locations
LocationPatentsSpan
Williston, VT, US172006–2019
Cambridge, VT, US21998–1999