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Inventor

Gerrit Jan Hemink

Inventor
Yokohama, JP

Overview

118→
Patents
1991–2021
Patent span
Physics
Primary field (CPC G)

Patents· 118 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores70%
H10BElectronic memory devices10%
H10DInorganic electric semiconductor devices7%
H01LSemiconductor devices4%
G06FElectric digital data processing4%
H10NElectric solid-state devices not otherwise provided for3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
11,101,326Methods of forming a phase change memory with vertical cross-point structure202111,088,206Methods of forming a phase change memory with vertical cross-point structure202111,081,198Non-volatile memory with countermeasure for over programming202111,011,242Bit line voltage control for damping memory programming202110,978,145Programming to minimize cross-temperature threshold voltage widening202110,978,156Concurrent programming of multiple cells for non-volatile memory devices202110,910,083Leaky memory hole repair at fabrication joint202110,839,928Non-volatile memory with countermeasure for over programming202010,748,622State adaptive predictive programming202010,643,720Bit line voltage control for damping memory programming202010,573,395Source voltage modulated reads in non-volatile memories202010,535,412Single pulse verification of memory cells202010,374,014Multi-state phase change memory device with vertical cross-point structure201910,304,551Erase speed based word line control201910,262,730Multi-state and confined phase change memory with vertical cross-point structure201910,008,273Cell current based bit line voltage20189,805,809'State-dependent read compensation'20179,564,226'Smart verify for programming non-volatile memory'20179,548,124'Word line dependent programming in a memory device'2017RE046264'Verification process for non-volatile storage'20179,530,504'Memory cells using multi-pass programming'20169,502,471'Multi tier three-dimensional memory devices including vertically shared bit lines'20169,443,606'Word line dependent two strobe sensing mode for nonvolatile storage elements'20169,355,713'Systems and methods for lower page writes'2016RE045954'Non-volatile storage with temperature compensation based on neighbor state information'2016RE045871'Selected word line dependent select gate voltage during program'20169,224,457'Non-volatile storage with temperature compensation based on neighbor state information'2015RE045754'Selective memory cell program and erase'2015RE045603'Detecting the completion of programming for non-volatile storage'20159,070,472'Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling'2015RE045544'Saw-shaped multi-pulse programming for program noise reduction in memory'20159,036,438'Non-volatile storage with temperature compensation based on neighbor state information'20158,902,652'Systems and methods for lower page writes'20148,804,430'Selected word line dependent select gate diffusion region voltage during programming'20148,782,495'Non-volatile memory and methods with asymmetric soft read points around hard read points'20148,755,234'Temperature based compensation during verify operations for non-volatile storage'20148,644,075'Ramping pass voltage to enhance channel boost in memory device'20148,638,608'Selected word line dependent select gate voltage during program'20148,605,513'Detecting the completion of programming for non-volatile storage'20138,593,871'Apparatus for reducing the impact of program disturb'20138,582,381'Temperature based compensation during verify operations for non-volatile storage'20138,542,530'Apparatus for reducing the impact of program disturb'20138,526,233'Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation'20138,498,152'Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling'20138,422,302'Programming non-volatile memory with variable initial programming pulse'20138,416,626'Detecting the completion of programming for non-volatile storage'20138,331,154'Apparatus for reducing the impact of program disturb'20128,315,093'Selective memory cell program and erase'20128,295,085'Programming non-volatile memory with high resolution variable initial programming pulse'20128,270,217'Apparatus for reducing the impact of program disturb'20128,254,177'Programming non-volatile memory with variable initial programming pulse'20128,223,554'Programming non-volatile memory with high resolution variable initial programming pulse'20128,223,556'Programming non-volatile memory with a reduced number of verify operations'20128,218,367'Verification process for non-volatile storage'20128,213,255'Non-volatile storage with temperature compensation based on neighbor state information'20128,189,378'Reducing program disturb in non-volatile storage'20128,184,478'Apparatus with reduced program disturb in non-volatile storage'20128,163,622'Method for angular doping of source and drain regions for odd and even NAND blocks'20128,144,511'Selective memory cell program and erase'20128,130,552'Multi-pass programming for memory with reduced data storage requirement'20128,116,140'Saw-shaped multi-pulse programming for program noise reduction in memory'20128,099,652'Non-volatile memory and methods with reading soft bits in non uniform schemes'20128,081,519'Adaptive erase and soft programming for memory'20118,054,691'Detecting the completion of programming for non-volatile storage'20118,045,375'Programming non-volatile memory with high resolution variable initial programming pulse'20118,014,205'System for verifying non-volatile storage using different voltages'20117,978,527'Verification process for non-volatile storage'20117,911,849'Controlled boosting in non-volatile memory soft programming'20117,911,846'Apparatus for reducing the impact of program disturb'20117,902,031'Method for angular doping of source and drain regions for odd and even NAND blocks'20117,843,739'System for verifying non-volatile storage using different voltages'20107,839,690'Adaptive erase and soft programming for memory'20107,796,433'Apparatus for reducing the impact of program disturb'20107,790,562'Method for angular doping of source and drain regions for odd and even NAND blocks'20107,773,414'Self-boosting system for flash memory cells'20107,719,902'Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage'20107,697,338'Systems for controlled boosting in non-volatile memory soft programming'20107,688,638'Faster programming of multi-level non-volatile storage through reduced verify operations'20107,672,165'Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices'20107,606,100'Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells'20097,596,031'Faster programming of highest multi-level state for non-volatile memory'20097,534,690'Non-volatile memory with asymmetrical doping profile'20097,535,763'Controlled boosting in non-volatile memory soft programming'20097,522,457'Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage'20097,515,463'Reducing the impact of program disturb during read'20097,499,326'Apparatus for reducing the impact of program disturb'20097,486,564'Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells'20097,471,566'Self-boosting system for flash memory cells'20087,468,918'Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data'20087,466,590'Self-boosting method for flash memory cells'20087,463,522'Non-volatile storage with boosting using channel isolation switching'20087,463,531'Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages'20087,460,404'Boosting for non-volatile storage using channel isolation switching'20087,457,163'System for verifying non-volatile storage using different voltages'20087,457,166'Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage'20087,450,430'Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages'20087,447,086'Selective program voltage ramp rates in non-volatile memory'20087,440,331'Verify operation for non-volatile storage using different voltages'20087,436,703'Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices'20087,436,713'Reducing the impact of program disturb'20087,433,241'Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data'20087,426,137'Apparatus for reducing the impact of program disturb during read'20087,408,804'Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells'20087,403,424'Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells'20087,400,537'Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells'20087,362,615'Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices'20087,355,888'Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages'20087,355,892'Partial page fail bit detection in flash memory devices'20087,355,889'Method for programming non-volatile memory with reduced program disturb using modified pass voltages'20087,304,893'Method of partial page fail bit detection in flash memory devices'20077,294,882'Non-volatile memory with asymmetrical doping profile'20077,295,478'Selective application of program inhibit schemes in non-volatile memory'20077,196,946'Compensating for coupling in non-volatile storage'20077,173,859'Faster programming of higher level states in multi-level cell flash memory'20077,161,833'Self-boosting system for flash memory cells'20077,092,290'High speed programming system with reduced over programming'20065,216,269'Electrically-programmable semiconductor memories with buried injector region'19935,017,978'EPROM having a reduced number of contacts'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–1993Based in Enschede, NL· patent location history
2006–2012Patents assigned to SANDISK CORP (50)· patent assignee history
2006–2017Based in Yokohama, JP· patent location history
2011–2017Patents assigned to SANDISK TECHNOLOGIES INC (46)· patent assignee history
2011–2015Patents assigned to HEMINK GERRIT JAN (28)· patent assignee history
2011–2014Patents assigned to LEE SHIH-CHUNG (6)· patent assignee history
2012–2014Based in Kanagawa, JP· patent location history
2014–2021Based in San Ramon, CA, US· patent location history
2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (22)· patent assignee history
2021Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK CORP502006–2012
SANDISK TECHNOLOGIES INC462011–2017
HEMINK GERRIT JANself282011–2015
SANDISK TECHNOLOGIES LLC222016–2021
LEE SHIH-CHUNG62011–2014
Locations
LocationPatentsSpan
Yokohama, JP892006–2017
San Ramon, California, US222014–2021
Kanagawa, JP32012–2014
Enschede, NL21991–1993
San Jose, California, US12021