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Inventor

Tse-Yu Yeh

Inventor
Milpitas, CA, US

Overview

42→
Patents
1998–2013
Patent span
Physics
Primary field (CPC G)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing95%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
8,566,528'Combining write buffer with dynamically adjustable flush metrics'20138,352,685'Combining write buffer with dynamically adjustable flush metrics'20138,255,670'Replay reduction for power saving'20128,171,240'Misalignment predictor'20128,171,326'L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down'20128,117,404'Misalignment predictor'20127,996,646'Efficient encoding for detecting load dependency on store with misalignment'20117,752,474'L1 cache flush when processor is entering low power mode'20107,721,066'Efficient encoding for detecting load dependency on store with misalignment'20107,647,518'Replay reduction for power saving'20107,269,714'Inhibiting of a co-issuing instruction in a processor having different pipeline lengths'20077,203,817'Power consumption reduction in a pipeline by stalling instruction issue on a load miss'20077,162,613'Mechanism for processing speculative LL and SC instructions in a pipelined processor'20077,100,064'Limiting performance in an integrated circuit to meet export restrictions'20066,976,152'Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard'20056,877,085'Mechanism for processing speclative LL and SC instructions in a pipelined processor'20056,871,275'Microprocessor having a branch predictor using speculative branch registers'20056,629,238'Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iteration'20036,611,910'Method for processing branch operations'20036,553,488'Method and apparatus for branch prediction using first and second level branch prediction tables'20036,542,981'Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode'20036,438,682'Method and apparatus for predicting loop exit branches'20026,430,674'Processor executing plural instruction sets (ISA\'s) with ability to have plural ISA\'s in different pipeline stages at same time'20026,427,206'Optimized branch predictions for strongly predicted compiler branches'20026,353,805'Apparatus and method for cycle accounting in microprocessors'20026,304,960'Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions'20016,282,636'Decentralized exception processing system'20016,253,315'Return address predictor that uses branch instructions to track a last valid return address'20016,240,510'System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions'20016,237,077'Instruction template for efficient processing clustered branch instructions'20016,212,603'Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory'20016,185,676'Method and apparatus for performing early branch prediction in a microprocessor'20016,092,188'Processor and instruction set with predict instructions'20006,052,802'Apparatus and method for cycle accounting in microprocessors'20006,044,456'Electronic system and method for maintaining synchronization of multiple front-end pipelines'20006,012,134'High-performance processor with streaming buffer that facilitates prefetching of instructions'20005,987,599'Target instructions prefetch cache'19995,903,750'Dynamic branch prediction for branch instructions with multiple targets'19995,815,700'Branch prediction table having pointers identifying other branches within common instruction cache lines'19985,805,878'Method and apparatus for generating branch predictions for multiple branch instructions indexed by a single instruction pointer'19985,802,602'Method and apparatus for performing reads of related data from a set-associative cache memory'19985,742,804'Instruction prefetch mechanism utilizing a branch predict instruction'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2005Patents assigned to INTEL CORP (20)· patent assignee history
1998–2001Patents assigned to INST THE DEV OF EMERGING ARCHI (4)· patent assignee history
1998–2007Based in Milpitas, CA, US· patent location history
2005–2007Patents assigned to BROADCOM CORP (6)· patent assignee history
2010–2013Patents assigned to APPLE INC (10)· patent assignee history
2010–2013Based in Cupertino, CA, US· patent location history
2012–2013Patents assigned to YEH TSE-YU (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP201998–2005
APPLE INC102010–2013
BROADCOM CORP62005–2007
YEH TSE-YUself52012–2013
INST THE DEV OF EMERGING ARCHI41998–2001
Locations
LocationPatentsSpan
Milpitas, California, US321998–2007
Cupertino, California, US102010–2013