Inventor

Charles L. Ingalls

Inventor

Meridian, ID, US

Overview

1995–2021

Patent span

Physics

Primary field (CPC G)

Patents· 107 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores52%

H10BElectronic memory devices14%

H10DInorganic electric semiconductor devices10%

H01LSemiconductor devices8%

G06FElectric digital data processing4%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

H03KPulse technique2%

H10NElectric solid-state devices not otherwise provided for2%

G01RMeasuring electric variables2%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%

PatentTitleYear

11,062,753Array data bit inversion2021 11,031,400Integrated memory comprising secondary access devices between digit lines and primary access devices2021 10,998,027Memory circuitry2021 10,957,681Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array2021 10,957,382Integrated assemblies comprising vertically-stacked memory array decks and folded digit line connections2021 10,943,642Integrated memory assemblies comprising multiple memory array decks2021 10,930,653Apparatuses comprising memory cells, and apparatuses comprising memory arrays2021 10,916,548Memory arrays with vertical access transistors2021 10,916,295Memory arrays with vertical thin film transistors coupled between digit lines2021 10,910,049Sub-word line driver circuit2021 10,910,038DRAM array architecture with row hammer stress mitigation2021 10,896,722Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure2021 10,896,706FX driver circuit2021 10,872,648Apparatuses and methods for reducing row address to column address delay2020 10,854,617Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors2020 10,811,083Integrated assemblies comprising supplemental sense-amplifier-circuitry for refresh2020 10,796,743Dynamic adjustment of memory cell digit line capacitance2020 10,783,949Half density ferroelectric memory and operation2020 10,748,596Array data bit inversion2020 10,726,907Electronic device with a sense amp mechanism2020 10,672,435Sense amplifier signal boost2020 10,672,456Three dimensional memory devices2020 10,658,024Systems and methods for dynamic random access memory (DRAM) cell voltage boosting2020 10,622,057Tri-level DRAM sense amplifer2020 10,614,874Integrated memory assemblies comprising multiple memory array decks2020 10,607,687Apparatuses and methods for sense line architectures for semiconductor memories2020 10,580,464Sense amplifier constructions2020 10,535,388Apparatuses and methods for reducing row address to column address delay2020 10,510,394Reprogrammable non-volatile ferroelectric latch for use with a memory controller2019 10,431,282Array data bit inversion2019 10,431,284Dynamic reference voltage determination2019 10,431,291Systems and methods for dynamic random access memory (DRAM) cell voltage boosting2019 10,403,388Plate defect mitigation techniques2019 10,372,566Storing memory array operational information in nonvolatile subarrays2019 10,366,738Integrated memory assemblies comprising multiple memory array decks2019 10,360,966Half density ferroelectric memory and operation2019 10,347,635Apparatuses comprising memory cells, and apparatuses comprising memory arrays2019 10,339,985Sense amplifier constructions2019 10,236,036Sense amplifier signal boost2019 10,163,483Dynamic reference voltage determination2018 10,153,024Dynamic adjustment of memory cell digit line capacitance2018 10,115,438Sense amplifier constructions2018 10,043,566Array data bit inversion2018 9,941,021Plate defect mitigation techniques2018 9,934,839Dynamic adjustment of memory cell digit line capacitance2018 9,892,776'Half density ferroelectric memory and operation'2018 9,858,979'Reprogrammable non-volatile ferroelectric latch for use with a memory controller'2018 9,847,117Dynamic reference voltage determination2017 9,786,348'Dynamic adjustment of memory cell digit line capacitance'2017 9,715,919'Array data bit inversion'2017 9,190,126'Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers'2015 9,159,392'Memory device word line drivers and methods'2015 9,147,473'Apparatuses and methods for driving a voltage of a wordline of a memory'2015 9,087,604'Pre-charging method applied in dynamic random access memories'2015 9,076,501'Apparatuses and methods for reducing current leakage in a memory'2015 9,070,425'Data line control for sense amplifiers'2015 8,737,157'Memory device word line drivers and methods'2014 8,598,912'Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers'2013 8,149,619'Memory structure having volatile and non-volatile memory portions'2012 7,986,578'Low voltage sense amplifier and sensing method'2011 7,898,857'Memory structure having volatile and non-volatile memory portions'2011 7,626,877'Low voltage sense amplifier and sensing method'2009 7,616,504'High speed array pipeline architecture'2009 7,535,282'Dynamic well bias controlled by Vt detector'2009 7,512,025'Open digit line array architecture for a memory array'2009 7,505,341'Low voltage sense amplifier and sensing method'2009 7,480,202'High speed array pipeline architecture'2009 7,460,430'Memory devices having reduced coupling noise between wordlines'2008 7,417,916'Methods of reducing coupling noise between wordlines'2008 7,352,649'High speed array pipeline architecture'2008 7,345,937'Open digit line array architecture for a memory array'2008 7,277,310'Open digit line array architecture for a memory array'2007 7,254,074'Open digit line array architecture for a memory array'2007 7,193,914'Open digit line array architecture for a memory array'2007 7,110,319'Memory devices having reduced coupling noise between wordlines'2006 6,949,952'Programming circuit and method having extended duration programming capabilities'2005 6,901,023'Word line driver for negative voltage'2005 6,836,427'System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems'2004 6,836,145'Programming circuit and method having extended duration programming capabilities'2004 6,754,131'Word line driver for negative voltage'2004 6,653,195'Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell'2003 6,536,004'On-chip circuit and method for testing memory devices'2003 6,429,449'Three-dimensional container diode for use with multi-state material in a non-volatile memory cell'2002 6,411,553'Single ended data bus equilibration scheme'2002 6,345,013'Latched row or column select enable driver'2002 6,345,006'Memory circuit with local isolation and pre-charge circuits'2002 6,333,882'Equilibration/pre-charge circuit for a memory device'2001 6,275,443'Latched row or column select enable driver'2001 6,246,623'Method and apparatus for strobing antifuse circuits in a memory device'2001 6,178,532'On-chip circuit and method for testing memory devices'2001 6,178,501'Method and apparatus for initializing a memory device'2001 6,118,135'Three-dimensional container diode for use with multi-state material in a non-volatile memory cell'2000 6,064,617'Method and apparatus for strobing antifuse circuits in a memory device'2000 5,985,698'Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell'1999 5,978,297'Method and apparatus for strobing antifuse circuits in a memory device'1999 5,978,285'Voltage-dependent delay'1999 5,964,896'Method and apparatus for a high speed cyclical redundancy check system'1999 5,936,901'Shared data lines for memory write and memory test operations'1999 5,892,716'Method and apparatus for global testing the impedance of a programmable element'1999 5,854,800'Method and apparatus for a high speed cyclical redundancy check system'1998 5,831,276'Three-dimensional container diode for use with multi-state material in a non-volatile memory cell'1998 5,805,931'Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols'1998 5,648,974'System having multiple subsystems and test signal source resident upon common substrate'1997 5,617,367'Controlling synchronous serial access to a multiport memory'1997 5,524,098'Controlling synchronous serial access to a multiport memory'1996 5,499,250'System having multiple subsystems and test signal source resident upon common substrate'1996 5,442,642'Test signal generator on substrate to test'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–1997Based in Boise, ID, US· patent location history

1996–2021Patents assigned to MICRON TECHNOLOGY INC (105)· patent assignee history

1998–2021Based in Meridian, ID, US· patent location history

2012–2014Patents assigned to KIRSCH HOWARD C (3)· patent assignee history

2012Patents assigned to INGALLS CHARLES (1)· patent assignee history

2012Patents assigned to JUENGLING WERNER (1)· patent assignee history

2013–2014Patents assigned to INGALLS CHARLES L (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	105	1996–2021
KIRSCH HOWARD C	3	2012–2014
INGALLS CHARLES Lself	2	2013–2014
INGALLS CHARLESself	1	2012
JUENGLING WERNER	1	2012

Locations

Location	Patents	Span
Meridian, ID, US	102	1998–2021
Boise, ID, US	5	1995–1997