Inventor
Ashwin Raghunathan
Inventor
Santa Clara, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses18%
G01NInvestigating or analysing materials by determining their chemical or physical properties15%
C12QMeasuring or testing processes involving enzymes, nucleic acids or microorganisms12%
G06FElectric digital data processing12%
C07CAcyclic or carbocyclic compounds9%
G01RMeasuring electric variables6%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes6%
H03KPulse technique6%
H04LTransmission of digital information, e.g. telegraphic communication6%
G04FTime-interval measuring3%
PatentTitleYear
10,956,128Application with embedded workflow designer202110,942,146Electrochemically active agents for pH modulation in biological buffers202110,846,153Bot creation with workflow development system202010,514,352High density electrode arrays with outlier behavior detection circuitry and methods therefor201910,379,080Electronic control of the pH of a solution close to an electrode surfaces201910,331,416Application with embedded workflow designer201910,041,905Electrochemically active agents for pH modulation in biological buffers201810,025,567Bot creation with workflow development system201810,011,549Electrochemically active agents for pH modulation in biological buffers20188,669,794'Circuit for detecting a voltage change using a time-to-digital converter'20148,362,848'Supply-regulated VCO architecture'20138,363,485'Delay line that tracks setup time of a latching element over PVT'20138,330,511'PLL charge pump with reduced coupling to bias nodes'20128,164,369'Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits'20128,159,888'Recalibration systems and techniques for electronic memory applications'20127,973,612'Supply-regulated phase-locked loop (PLL) and method of using'20117,932,757'Techniques for minimizing control voltage ripple due to charge pump leakage in phase locked loop circuits'20117,880,554'Periodic timing jitter reduction in oscillatory systems'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2014Patents assigned to QUALCOMM INC (9)· patent assignee history
2011–2013Based in Santa Clara, CA, US· patent location history
2012–2014Patents assigned to RAGHUNATHAN ASHWIN (6)· patent assignee history
2012–2014Patents assigned to PEDRALI-NOY MARZIO (5)· patent assignee history
2014Based in Mountain View, CA, US· patent location history
2018–2021Patents assigned to BOSCH GMBH ROBERT (5)· patent assignee history
2018–2021Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (4)· patent assignee history
2018–2021Based in San Francisco, CA, US· patent location history
2018–2021Based in Bellevue, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 9 | 2011–2014 |
| RAGHUNATHAN ASHWINself | 6 | 2012–2014 |
| BOSCH GMBH ROBERT | 5 | 2018–2021 |
| PEDRALI-NOY MARZIO | 5 | 2012–2014 |
| MICROSOFT TECHNOLOGY LICENSING LLC | 4 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 8 | 2011–2013 |
| San Francisco, California, US | 5 | 2018–2021 |
| Bellevue, Washington, US | 4 | 2018–2021 |
| Mountain View, California, US | 1 | 2014 |