Inventor
Taketo Heishi
Inventor
Osaka, JP
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing89%
H03KPulse technique2%
H04BTransmission2%
H04MTelephonic communication2%
H04NPictorial communication, e.g. television2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
RE045199'Compiler apparatus'20148,612,958'Program converting apparatus and program conversion method'20138,587,336'Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block'20138,418,157'Compiler apparatus with flexible optimization'20138,402,445'Program translation method and notifying instruction inserting method'20138,392,905'Compiling apparatus'20138,286,145'Program re-writing apparatus'20128,151,254'Compiler, compiler apparatus and compilation method'20127,877,743'Program translation method and notifying instruction inserting method'20117,856,629'Compiler apparatus'20107,823,142'Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor'2010RE041751'Instruction converting apparatus using parallel execution code'20107,761,692'Processor, compiler and compilation method'20107,698,696'Compiler apparatus with flexible optimization'20107,689,976'Compiler apparatus and linker apparatus'20107,594,099'Processor executing SIMD instructions'20097,571,432'Compiler apparatus for optimizing high-level language programs using directives'20097,424,578'Computer system, compiler apparatus, and operating system'20087,386,844'Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions'20087,380,112'Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags'20087,284,241'Compiler, compiler apparatus and compilation method'20077,281,117'Processor executing SIMD instructions'20077,254,807'Program conversion apparatus, program conversion method, and computer program for executing program conversion process'20077,237,229'Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration'20077,185,176'Processor executing SIMD instructions'20077,185,324'Compiler apparatus and method for determining locations for data in memory area'20077,080,367'Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor'20067,076,638'Processor, compiler and compilation method'20067,073,169'Compiler device with branch instruction inserting unit'20066,976,245'PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR'20056,976,250'Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor'20056,904,135'Compound device and telephone station device connected to the same, and power supply system and portable telephone system using compound device'20056,880,150'PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR'20056,820,223'Processor, compiling apparatus, and compile program recorded on a recording medium'20046,760,906'METHOD AND SYSTEM FOR PROCESSING PROGRAM FOR PARALLEL PROCESSING PURPOSES, STORAGE MEDIUM HAVING STORED THEREON PROGRAM GETTING PROGRAM PROCESSING EXECUTED FOR PARALLEL PROCESSING PURPOSES, AND STORAGE MEDIUM HAVING STORED THEREON INSTRUCTION SET TO BE EXECUTED IN PARALLEL'20046,606,703'Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions'20036,490,673'Processor, compiling apparatus, and compile program recorded on a recording medium'20026,324,639'Instruction converting apparatus using parallel execution code'20016,230,258'Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions'20016,219,779'Constant reconstructing processor which supports reductions in code size'20016,209,080'Constant reconstruction processor that supports reductions in code size and processing time'20016,195,740'Constant reconstructing processor that execute an instruction using an operand divided between instructions'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2008Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (25)· patent assignee history
2001–2014Based in Osaka, JP· patent location history
2009–2014Patents assigned to PANASONIC CORP (16)· patent assignee history
2012–2014Patents assigned to HEISHI TAKETO (8)· patent assignee history
2012–2014Patents assigned to OGAWA HAJIME (4)· patent assignee history
2013–2014Patents assigned to MICHIMOTO SHOHEI (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MATSUSHITA ELECTRIC INDUSTRIAL CO LTD | 25 | 2001–2008 |
| PANASONIC CORP | 16 | 2009–2014 |
| HEISHI TAKETOself | 8 | 2012–2014 |
| MICHIMOTO SHOHEI | 4 | 2013–2014 |
| OGAWA HAJIME | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Osaka, JP | 42 | 2001–2014 |