Inventor
John M. Birkner
Inventor
Woodside, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique43%
G06FElectric digital data processing11%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems11%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G05FSystems for regulating electric or magnetic variables5%
G11CStatic stores3%
H03GControl of amplification3%
H03MCoding3%
B05BSpraying apparatus1%
PatentTitleYear
10,447,276Power management integrated circuit integrating field effect transistors and programmable fabric201910,425,082Adaptive analog blocks with digital wrappers integrated onto programmable fabric201910,396,800Compensation memory (CM) for power application201910,320,391Pulse-width modulation (PWM) control loop for power application201910,312,911Programmable analog and digital input/output for power application201910,291,229Programmable logic device with integrated high voltage power FET201910,200,056Method and apparatus for analog to digital error conversion with multiple symmetric transfer functions201910,200,040Precision modulation timer (PMT) integrated in a programmable logic device201910,171,085Noise-immune reference (NREF) integrated in a programmable logic device201910,141,937Pulse-width modulation (PWM) control loop for power application201810,135,447Compensation memory (CM) for power application201810,063,237Scalable integrated MOSFET (SIM)201810,029,273End effector cleaning devices and systems201810,003,338Programmable analog and digital input/output for power application20189,998,135Method and apparatus for analog to digital error conversion with multiple symmetric transfer functions20189,979,395Precision modulation timer (PMT) integrated in a programmable logic device20189,954,535Noise-immune reference (NREF) integrated in a programmable logic device20189,887,699'Programmable logic device with integrated high voltage power FET'20188,044,682'FPGA having low power, fast carry chain'20116,150,199'Method for fabrication of programmable interconnect structure'20006,078,191'Programmable application specific integrated circuit and logic cell'20005,989,943'Method for fabrication of programmable interconnect structure'19995,986,468'Programmable application specific integrated circuit and logic cell therefor'19995,780,919'Electrically programmable interconnect structure having a PECVD amorphous silicon element'19985,726,586'Programmable application specific integrated circuit and logic cell therefor'19985,717,230'Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses'19985,594,364'Programmable application specific integrated circuit and logic cell therefor'19975,587,669'Programmable application specific integrated circuit and logic cell therefor'19965,502,315'Electrically programmable interconnect structure having a PECVD amorphous silicon element'19965,430,390'Programmable application specific integrated circuit and logic cell therefor'19955,416,367'Programmable application specific integrated circuit and logic cell therefor'19955,293,133'Method of determining an electrical characteristic of an antifuse and apparatus therefor'19945,280,202'Programmable application specific integrated circuit and logic cell therefor'19945,122,685'Programmable application specific integrated circuit and logic cell therefor'19924,933,577'Output circuit for a programmable logic array'19904,862,136'Programmable resistance network'19894,789,951'Programmable array logic cell'19884,758,746'Programmable logic array with added array of gates and added output routing flexibility'19884,554,640'Programmable array logic circuit with shared product terms'19854,476,560'Diagnostic circuit for digital systems'19844,238,833'High-speed digital bus-organized multiplier/divider system'19804,153,938'High speed combinatorial digital multiplier'19794,124,899'Programmable array logic circuit'1978Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1978–1988Patents assigned to MONOLITHIC MEMORIES INC (6)· patent assignee history
1978–1979Based in Santa Clara, CA, US· patent location history
1980–1989Based in Sunnyvale, CA, US· patent location history
1984–1990Patents assigned to ADVANCED MICRO DEVICES INC (3)· patent assignee history
1989Patents assigned to BIRKNER JOHN M (1)· patent assignee history
1990–2000Based in Portola Valley, CA, US· patent location history
1992–2000Patents assigned to QUICKLOGIC CORP (15)· patent assignee history
1996–2019Based in Woodside, CA, US· patent location history
2018–2019Patents assigned to ANDAPT INC (17)· patent assignee history
2018Based in Evansville, IN, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ANDAPT INC | 17 | 2018–2019 |
| QUICKLOGIC CORP | 15 | 1992–2000 |
| MONOLITHIC MEMORIES INC | 6 | 1978–1988 |
| ADVANCED MICRO DEVICES INC | 3 | 1984–1990 |
| BIRKNER JOHN Mself | 1 | 1989 |
Locations
| Location | Patents | Span |
|---|---|---|
| Woodside, California, US | 19 | 1996–2019 |
| Portola Valley, California, US | 15 | 1990–2000 |
| Sunnyvale, California, US | 6 | 1980–1989 |
| Santa Clara, California, US | 2 | 1978–1979 |
| Evansville, IN, US | 1 | 2018 |