Inventor

Sansaptak Dasgupta

Inventor

Hillsboro, OR, US

Overview

2014–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 110 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices30%

H10DInorganic electric semiconductor devices30%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

H03HImpedance networks, e.g. resonant circuits2%

B82YSpecific uses or applications of nanostructures1%

H10NElectric solid-state devices not otherwise provided for1%

H10BElectronic memory devices1%

H10HInorganic light-emitting semiconductor devices having potential barriers1%

H03FAmplifiers1%

PatentTitleYear

11,118,117Regulatory controller for usage in a catalytic olefins2021 10,879,346Capacitor including multilayer dielectric stack2020 10,879,134Techniques for monolithic co-integration of silicon and III-N semiconductor transistors2020 10,861,942Tunable capacitors including III-N multi-2DEG and 3DEG structures for tunable RF filters2020 10,850,977Group III-N MEMS structures on a group IV substrate2020 10,847,624Methods and apparatus to form GaN-based transistors during back-end-of-the-line processing2020 10,848,127Film bulk acoustic resonator (FBAR) RF filter having epitaxial layers2020 10,840,341Semiconductor devices, radio frequency devices and methods for forming semiconductor devices2020 10,811,526Stacked group III-nitride transistors for an RF switch and methods of fabrication2020 10,811,501InN tunnel junction contacts for P-channel GaN2020 10,804,879Film bulk acoustic resonator (FBAR) devices for high frequency RF filters2020 10,804,214Group III-N material conductive shield for high frequency metal interconnects2020 10,804,386Gate stack design for GaN e-mode transistor performance2020 10,804,359Geometric manipulation of 2DEG region in source/drain extension of GaN transistor2020 10,790,332Techniques for integrating three-dimensional islands for radio frequency (RF) circuits2020 10,777,671Layered spacer formation for ultrashort channel lengths and staggered field plates2020 10,777,672Gallium nitride transistors for high-voltage radio frequency switches2020 10,770,575Vertical group III-N devices and their methods of fabrication2020 10,770,551P-I-N diode and connected group III-N device and their methods of fabrication2020 10,763,248Multi-layer silicon/gallium nitride semiconductor2020 10,763,350Transistor connected diodes and connected III-N devices and their methods of fabrication2020 10,756,183N-channel gallium nitride transistors2020 10,727,2413D NAND structures including group III-N material channels2020 10,727,339Selectively regrown top contact for vertical semiconductor devices2020 10,720,505Ferroelectric-based field-effect transistor with threshold voltage switching for enhanced on-state and off-state performance2020 10,707,136Gallium nitride NMOS on Si (111) co-integrated with a silicon PMOS2020 10,700,665Film bulk acoustic resonator (FBAR) devices for high frequency RF filters2020 10,692,839GaN devices on engineered silicon substrates2020 10,673,405Film bulk acoustic resonator (FBAR) devices with 2DEG bottom electrode2020 10,672,884Schottky diodes on semipolar planes of group III-N material structures2020 10,665,708Semiconductor devices with raised doped crystalline structures2020 10,665,707Techniques for co-integrating transition metal dichalcogenide (TMDC)-based and III-N semiconductor-based transistor devices2020 10,665,577Co-integrated III-N voltage regulator and RF power amplifier for envelope tracking systems2020 10,658,502Vertical III-N transistors with lateral overgrowth over a protruding III-N semiconductor structure2020 10,658,471Transition metal dichalcogenides (TMDCS) over III-nitride heteroepitaxial layers2020 10,658,475Transistors with vertically opposed source and drain metal interconnect layers2020 10,622,448Transistors including retracted raised source/drain to reduce parasitic capacitances2020 10,600,787Silicon PMOS with gallium nitride NMOS for voltage regulation2020 10,586,866Stressors for compressively strained GaN p-channel2020 10,580,895Wide band gap transistors on non-native semiconductor substrates2020 10,573,647CMOS circuits using n-channel and p-channel gallium nitride transistors2020 10,574,187Envelope-tracking control techniques for highly-efficient RF power amplifiers2020 10,553,689Multiple stacked field-plated GaN transistor and interlayer dielectrics to improve breakdown voltage and reduce parasitic capacitances2020 10,546,927Self-aligned transistor structures enabling ultra-short channel lengths2020 10,535,777Nanoribbon structures with recessed source-drain epitaxy2020 10,497,785Gallium nitride voltage regulator2019 10,475,888Integration of III-V devices on Si wafers2019 10,475,706Making a defect free fin based device in lateral epitaxy overgrowth region2019 10,453,679Methods and devices integrating III-N transistor circuitry with Si transistor circuitry2019 10,439,057Multi-gate high electron mobility transistors and methods of fabrication2019 10,431,717Light-emitting diode (LED) and micro LED substrates and methods for making the same2019 10,411,067Integrated RF frontend structures2019 10,388,777Heteroepitaxial structures with high temperature stable substrate interface material2019 10,347,834Wafer-scale integration of vacancy centers for spin qubits2019 10,347,544Co-planar p-channel and n-channel gallium nitride-based transistors on silicon and techniques for forming same2019 10,332,998Transistors with heteroepitaxial III-N source/drain2019 10,325,774Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2019 10,249,490Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy2019 10,243,069Gallium nitride transistor having a source/drain structure including a single-crystal portion abutting a 2D electron gas2019 10,229,991III-N epitaxial device structures on free standing silicon mesas2019 10,217,673Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith2019 10,211,327Semiconductor devices with raised doped crystalline structures2019 10,204,989Method of fabricating semiconductor structures on dissimilar substrates2019 10,170,612Epitaxial buffer layers for group III-N transistors on silicon substrates2019 10,134,727High breakdown voltage III-N depletion mode MOS capacitors2018 10,096,683Group III-N transistor on nanoscale template structures2018 10,096,474Methods and structures to prevent sidewall defects during selective epitaxy2018 10,096,682III-N devices in Si trenches2018 10,056,456N-channel gallium nitride transistors2018 10,050,015Multi-device flexible electronics system on a chip (SOC) process integration2018 10,032,911Wide band gap transistor on non-native semiconductor substrate2018 9,972,686Germanium tin channel transistors2018 9,935,191High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer2018 9,923,087'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2018 9,922,826'Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith'2018 9,905,651'GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2018 9,865,684'Nanoscale structure with epitaxial film having a recessed bottom portion'2018 9,847,432Forming III-V device structures on (111) planes of silicon fins2017 9,847,448Forming LED structures on silicon fins2017 9,837,499Self-aligned gate last III-N transistors2017 9,806,203'Nonplanar III-N transistors with compositionally graded semiconductor channels'2017 9,748,371'Transition metal dichalcogenide semiconductor assemblies'2017 9,716,149'Group III-N transistors on nanoscale template structures'2017 9,698,013'Methods and structures to prevent sidewall defects during selective epitaxy'2017 9,698,222'Method of fabricating semiconductor structures on dissimilar substrates'2017 9,673,045'Integration of III-V devices on Si wafers'2017 9,666,708'III-N transistors with enhanced breakdown voltage'2017 9,660,085'Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof'2017 9,660,067'III-N transistors with epitaxial layers providing steep subthreshold swing'2017 9,660,064'Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack'2017 9,640,422'III-N devices in Si trenches'2017 9,640,537'Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy'2017 9,634,007'Trench confined epitaxially grown device layer(s)'2017 9,590,069'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2017 9,583,396'Making a defect free fin based device in lateral epitaxy overgrowth region'2017 9,583,574'Epitaxial buffer layers for group III-N transistors on silicon substrates'2017 9,570,614'Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2017 9,391,181'Lattice mismatched hetero-epitaxial film'2016 9,373,693'Nonplanar III-N transistors with compositionally graded semiconductor channels'2016 9,362,369'Group III-N transistors on nanoscale template structures'2016 9,219,079'Group III-N transistor on nanoscale template structures'2015 9,099,490'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2015 9,064,709'High breakdown voltage III-N depletion mode MOS capacitors'2015 9,029,835'Epitaxial film on nanoscale structure'2015 8,954,021'Group III-N transistors on nanoscale template structures'2015 8,896,101'Nonplanar III-N transistors with compositionally graded semiconductor channels'2014 8,872,225'Defect transferred and lattice mismatched epitaxial film'2014 8,785,907'Epitaxial film growth on patterned substrate'2014 8,768,271'Group III-N transistors on nanoscale template structures'2014 8,765,563'Trench confined epitaxially grown device layer(s)'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2020Patents assigned to INTEL CORP (109)· patent assignee history

2014–2018Patents assigned to DASGUPTA SANSAPTAK (10)· patent assignee history

2014–2017Patents assigned to CHAU ROBERT S (9)· patent assignee history

2014–2018Patents assigned to RADOSAVLJEVIC MARKO (9)· patent assignee history

2014–2018Patents assigned to THEN HAN WUI (9)· patent assignee history

2014–2020Based in Hillsboro, OR, US· patent location history

2014–2019Based in Santa Clara, CA, US· patent location history

2020Based in Hillsborough, OR, US· patent location history

2021Based in Houston, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	109	2014–2020
DASGUPTA SANSAPTAKself	10	2014–2018
CHAU ROBERT S	9	2014–2017
RADOSAVLJEVIC MARKO	9	2014–2018
THEN HAN WUI	9	2014–2018

Locations

Location	Patents	Span
Hillsboro, OR, US	97	2014–2020
Santa Clara, California, US	9	2014–2019
Hillsborough, OR, US	3	2020
Houston, Texas, US	1	2021