LexDanaLexDanabeta
Inventor

Nanseng Jeng

Inventor
Boise, ID, US

Overview

52→
Patents
1995–2005
Patent span
Electricity
Primary field (CPC H)

Patents· 52 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H10DInorganic electric semiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices7%
H10BElectronic memory devices6%
PatentTitleYear
6,936,897'Intermediate structure having a silicon barrier layer encapsulating a semiconductor substrate'20056,930,363'Barrier in gate stack for improved gate dielectric integrity'20056,917,411'Method for optimizing printing of an alternating phase shift mask having a phase shift error'20056,835,634'Streamlined field isolation process'20046,809,395'Isolation structure having trench structures formed on both side of a locos'20046,770,571'Barrier in gate stack for improved gate dielectric integrity'20046,762,475'Semiconductor wafer isolation structure formed by field oxidation'20046,611,038'Semiconductor wafer isolation structure formed by field oxidation'20036,562,730'Barrier in gate stack for improved gate dielectric integrity'20036,472,280'Method for forming a spacer for semiconductor manufacture'20026,432,619'Method for reducing photolithographic steps in a semiconductor interconnect process'20026,373,114'Barrier in gate stack for improved gate dielectric integrity'20026,365,490'Process to improve the flow of oxide during field oxidation by fluorine doping'20026,337,172'Method for reducing photolithographic steps in a semiconductor interconnect process'20026,245,671'Semiconductor processing method of forming an electrically conductive contact plug'20016,232,191'Method for forming a spacer for semiconductor manufacture'20016,225,174'Method for forming a spacer using photosensitive material'20016,221,564'Method for forming a spacer out of photosensitive material'20016,127,096'Method for reducing photolithographic steps in a semiconductor interconnect process'20006,114,218'Texturized polycrystalline silicon to aid field oxide formation'20006,103,595'Assisted local oxidation of silicon'20006,090,685'Method of forming a LOCOS trench isolation structure'20006,077,740'Method for forming a semiconductor device contact structure comprising a contour'20006,069,059'Well-drive anneal technique using preplacement of nitride films for enhanced field isolation'20005,972,569'Method for reducing photolithographic steps in a semiconductor interconnect process'19995,963,820'Method for forming field oxide or other insulators during the formation of a semiconductor device'19995,940,692'Method of forming a field effect transistor'19995,933,754'Semiconductor processing method of forming an electrically conductive contact plug'19995,902,128'Process to improve the flow of oxide during field oxidation by fluorine doping'19995,891,788'Locus isolation technique using high pressure oxidation (hipox) and protective spacers'19995,888,881'Method of trench isolation during the formation of a semiconductor device'19995,837,378'Method of reducing stress-induced defects in silicon'19985,837,596'Field oxide formation by oxidation of polysilicon layer'19985,798,280'Process for doping hemispherical grain silicon'19985,753,962'Texturized polycrystalline silicon to aid field oxide formation'19985,741,624'Method for reducing photolithographic steps in a semiconductor interconnect process'19985,726,092'Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate'19985,719,418'Contact-substrate for a semiconductor device comprising a contour'19985,702,986'Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges'19975,674,776'Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate'19975,661,073'Method for forming field oxide having uniform thickness'19975,661,072'Method for reducing oxide thinning during the formation of a semiconductor device'19975,658,829'Semiconductor processing method of forming an electrically conductive contact plug'19975,637,514'Method of forming a field effect transistor'19975,629,230'Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion'19975,612,248'Method for forming field oxide or other insulators during the formation of a semiconductor device'19975,580,821'Semiconductor processing method of forming an electrically conductive contact plug'19965,508,215'Current leakage reduction at the storage node diffusion region of a stacked-trench dram cell by selectively oxidizing the floor of the trench'19965,492,853'Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device'19965,472,904'Thermal trench isolation'19955,438,016'Method of semiconductor device isolation employing polysilicon layer for field oxide formation'19955,416,348'Current leakage reduction at the storage node diffusion region of a stacked-trench DRAM cell by selectively oxidizing the floor of the trench'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2005Patents assigned to MICRON TECHNOLOGY INC (47)· patent assignee history
1995–1996Patents assigned to MICRON SEMICONDUCTOR INC (3)· patent assignee history
1995–2005Based in Boise, ID, US· patent location history
2000Patents assigned to MICROM TECHNOLOGY INC (1)· patent assignee history
2000–2005Based in Vancouver, WA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC471995–2005
MICRON SEMICONDUCTOR INC31995–1996
MICROM TECHNOLOGY INC12000
Locations
LocationPatentsSpan
Boise, ID, US461995–2005
Vancouver, Washington, US62000–2005