Inventor
Soummya Mallick
Inventor
Austin, TX, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing96%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
PatentTitleYear
6,212,542'Method and system for executing a program within a multiscalar processor by processing linked thread descriptors'20016,061,777'Apparatus and method for reducing the number of rename registers required in the operation of a processor'20005,995,743'Method and system for interrupt handling during emulation in a data processing system'19995,961,639'Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution'19995,956,495'Method and system for processing branch instructions during emulation in a data processing system'19995,953,520'Address translation buffer for data processing system emulation mode'19995,913,925'Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order'19995,913,054'Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle'19995,897,654'Method and system for efficiently fetching from cache during a cache fill operation'19995,897,655'System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference'19995,897,666'Generation of unique address alias for memory disambiguation buffer to avoid false collisions'19995,898,864'Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors'19995,887,166'Method and system for constructing a program including a navigation instruction'19995,872,948'Processor and method for out-of-order execution of instructions based upon an instruction parameter'19995,870,616'System and method for reducing power consumption in an electronic circuit'19995,870,575'Indirect unconditional branches in data processing system emulation mode'19995,870,577'System and method for dispatching two instructions to the same execution unit in a single cycle'19995,867,684'Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction'19995,850,563'Processor and method for out-of-order completion of floating-point operations during load/store multiple operations'19985,812,812'Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue'19985,812,823'Method and system for performing an emulation context save and restore that is transparent to the operating system'19985,809,323'Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor'19985,805,916'Method and apparatus for dynamic allocation of registers for intermediate floating-point results'19985,805,907'System and method for reducing power consumption in an electronic circuit'19985,802,556'Method and apparatus for correcting misaligned instruction data'19985,802,340'Method and system of executing speculative store instructions in a parallel processing computer system'19985,802,386'Latency-based scheduling of instructions in a superscalar processor'19985,802,572'Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache'19985,787,479'Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation'19985,764,940'Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch'19985,765,191'Method for implementing a four-way least recently used (LRU) mechanism in high-performance'19985,764,969'Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization'19985,765,215'Method and system for efficient rename buffer deallocation within a processor'19985,758,117'Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor'19985,758,140'Method and system for emulating instructions by performing an operation directly using special-purpose register contents'19985,758,141'Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register'19985,754,811'Instruction dispatch queue for improved instruction cache to queue timing'19985,752,014'Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction'19985,732,235'Method and system for minimizing the number of cycles required to execute semantic routines'19985,717,587'Method and system for recording noneffective instructions within a data processing system'19985,694,565'Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions'19975,664,120'Method for executing instructions and execution unit instruction reservation table within an in-order completion processor'19975,619,408'Method and system for recoding noneffective instructions within a data processing system'19975,611,063'Method for executing speculative load instructions in high-performance processors'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2001Patents assigned to IBM (43)· patent assignee history
1997–1999Patents assigned to MOTOROLA INC (10)· patent assignee history
1997–2001Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 43 | 1997–2001 |
| MOTOROLA INC | 10 | 1997–1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 44 | 1997–2001 |