Inventor
Po-Ching Hsu
Inventor
Hsinchu, TW
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables55%
G06FElectric digital data processing38%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
9,678,156'Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test'20179,316,688'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test'20169,274,168'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test'20169,091,730'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test'20159,057,763'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test'20159,046,572'Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults'20159,026,875'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test'20158,769,359'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test'20148,329,517'Pixel structure and method for manufacturing the same'20127,779,323'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test'20107,444,567'Method and apparatus for unifying self-test with scan-test during prototype debug and production test'20087,434,126'Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults'20087,284,175'Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques'20077,260,756'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test'20077,191,373'Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques'20077,058,869'Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits'20067,007,213'Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2016Patents assigned to SYNTEST TECHNOLOGIES INC (15)· patent assignee history
2006–2017Based in Hsinchu, TW· patent location history
2012Patents assigned to CHIMEI INNOLUX CORP (1)· patent assignee history
2012Patents assigned to HSU PO-CHING (1)· patent assignee history
2012Based in Miaoli, TW· patent location history
2017Patents assigned to SYNTEST TECH INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SYNTEST TECHNOLOGIES INC | 15 | 2006–2016 |
| CHIMEI INNOLUX CORP | 1 | 2012 |
| HSU PO-CHINGself | 1 | 2012 |
| SYNTEST TECH INC | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 16 | 2006–2017 |
| Miaoli, TW | 1 | 2012 |