Inventor
Mosur K. Ravishankar
Inventor
Mountain View, CA, US
Overview
Patents· 12 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing73%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
G09BEducational or demonstration appliances7%
G10LSpeech analysis techniques or speech synthesis7%
PatentTitleYear
8,744,856'Computer implemented system and method and computer program product for evaluating pronunciation of phonemes in a language'20147,389,389'System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system'20086,925,537'Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants'20056,751,720'Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy'20046,751,710'Scalable multiprocessor system and cache coherence method'20046,748,498'Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector'20046,697,919'System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system'20046,675,265'Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants'20046,640,287'Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests'20036,636,949'System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing'20036,622,218'Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system'20036,622,217'Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2008Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (11)· patent assignee history
2003–2008Based in Mountain View, CA, US· patent location history
2014Patents assigned to Carnegie Speech Company (1)· patent assignee history
2014Patents assigned to RAVISHANKAR MOSUR K (1)· patent assignee history
2014Based in Mars, PA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEWLETT PACKARD DEVELOPMENT CO | 11 | 2003–2008 |
| Carnegie Speech Company | 1 | 2014 |
| RAVISHANKAR MOSUR Kself | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 11 | 2003–2008 |
| Mars, Pennsylvania, US | 1 | 2014 |