Inventor
Irfan Rahim
Inventor
Milpitas, CA, US
Overview
Patents· 78 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique19%
G11CStatic stores19%
H10DInorganic electric semiconductor devices19%
G06FElectric digital data processing8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10BElectronic memory devices7%
H01LSemiconductor devices6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
11,079,282Flexible interconnect sensing devices and related methods202110,964,705Method of forming a semiconductor device20219,812,555'Bottom-gate thin-body transistors for stacked wafer integrated circuits'20179,761,624'Pixels for high performance image sensor'20179,564,464'Monolithically stacked image sensors'20179,520,182'Memory elements with relay devices'20169,496,268'Integrated circuits with asymmetric and stacked transistors'20169,455,715'Apparatus for improving reliability of electronic circuitry and associated methods'20169,425,192'Integrated circuit decoupling capacitors'20169,412,436'Memory elements with soft error upset immunity'20169,230,048'Integrated circuits with interconnect selection circuitry'20169,165,640'Method of using a PMOS pass gate'20158,995,175'Memory circuit with PMOS access transistors'20158,921,170'Integrated circuits with asymmetric pass transistors'20148,854,080'Integrated circuits with interconnect selection circuitry'20148,804,407'PMOS pass gate'20148,797,790'Memory elements with soft error upset immunity'20148,750,026'Integrated circuits with asymmetric and stacked transistors'20148,711,614'Memory elements with increased write margin and soft error upset immunity'20148,704,313'Low capacitance, low on resistance ESD diode'20148,698,516'Apparatus for improving performance of field programmable gate arrays and associated methods'20148,643,108'Buffered finFET device'20148,633,731'Programmable integrated circuit with thin-oxide passgates'20148,611,137'Memory elements with relay devices'20138,542,032'Integrated circuits with interconnect selection circuitry'20138,502,558'Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks'20138,482,963'Integrated circuits with asymmetric and stacked transistors'20138,461,869'Apparatus for configuring performance of field programmable gate arrays and associated methods'20138,369,175'Memory elements with voltage overstress protection'20138,289,755'Volatile memory elements with soft error upset immunity'20128,138,786'Apparatus and methods for adjusting performance of integrated circuits'20128,138,797'Integrated circuits with asymmetric pass transistors'20128,089,744'Apparatus and methods for electrostatic discharge circuitry with snap-back device'20128,081,502'Memory elements with body bias control'20118,072,237'Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks'20118,030,962'Configuration random access memory'20117,920,410'Memory elements with increased write margin and soft error upset immunity'20117,902,611'Integrated circuit well isolation structures'20117,858,469'Method for forming a trigger device for ESD protection circuit'20107,800,400'Configuration random access memory'20107,800,402'Look-up table overdrive circuits'20107,741,716'Integrated circuit bond pad structures'20107,639,033'On-chip voltage regulator using feedback on process/product parameters'20097,612,410'Trigger device for ESD protection circuit'20097,573,317'Apparatus and methods for adjusting performance of integrated circuits'20097,465,971'Integrated circuit structures for increasing resistance to single event upset'20087,463,057'Integrated circuits with adjustable memory element power supplies'20087,400,480'Electrostatic discharge protection circuit'20087,361,961'Method and apparatus with varying gate oxide thickness'20087,352,610'Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits'20087,348,827'Apparatus and methods for adjusting performance of programmable logic devices'20087,321,236'Apparatus and methods for programmable logic devices with improved performance characteristics'20087,319,253'Integrated circuit structures for increasing resistance to single event upset'20087,291,546'Method and apparatus for reducing charge loss in a nonvolatile memory cell'20077,277,346'Method and system for hard failure repairs in the field'20077,271,989'Electrostatic discharge protection circuit'20077,242,218'Techniques for combining volatile and non-volatile programmable logic on an integrated circuit'20077,210,115'Methods for optimizing programmable logic device performance by reducing congestion'20077,200,824'Performance/power mapping of a die'20077,183,800'Apparatus and methods for programmable logic devices with improved performance characteristics'20077,173,320'High performance lateral bipolar transistor'20077,170,308'On-chip voltage regulator using feedback on process/product parameters'20077,153,712'Electrically-programmable integrated circuit fuses and sensing circuits'20067,142,009'Adaptive power supply voltage regulation for programmable logic'20067,139,997'Method and system for checking operation of a mask generation algorithm'20067,135,951'Integrated circuit inductors'20067,129,745'Apparatus and methods for adjusting performance of integrated circuits'20066,963,503'EEPROM with improved circuit performance and reduced cell size'20056,933,591'Electrically-programmable integrated circuit fuses and sensing circuits'20056,773,987'Method and apparatus for reducing charge loss in a nonvolatile memory cell'20046,670,676'Hot socket soft pull for ESD devices'20036,476,635'Programmable number of metal lines and effective metal width along critical paths in a programmable logic device'20026,362,525'Circuit structure including a passive element formed within a grid array substrate and method for making the same'20026,207,991'Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same'20016,124,157'Integrated non-volatile and random access memory and method of forming the same'20006,069,382'Non-volatile memory cell having a high coupling ratio'20005,900,763'Circuit and method of reducing cross-talk in an integrated circuit substrate'19995,405,790'Method of forming a semiconductor structure having MOS, bipolar, and varactor devices'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Based in Chandler, AZ, US· patent location history
1999Based in Selanger, MY· patent location history
2000–2021Based in Milpitas, CA, US· patent location history
2004–2016Patents assigned to ALTERA CORP (64)· patent assignee history
2005–2014Based in San Jose, CA, US· patent location history
2011–2016Patents assigned to RAHIM IRFAN (23)· patent assignee history
2011–2015Patents assigned to LEE ANDY L (11)· patent assignee history
2011–2015Patents assigned to LIU JUN (7)· patent assignee history
2012–2014Patents assigned to WATT JEFFREY T (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 64 | 2004–2016 |
| RAHIM IRFANself | 23 | 2011–2016 |
| LEE ANDY L | 11 | 2011–2015 |
| WATT JEFFREY T | 8 | 2012–2014 |
| LIU JUN | 7 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Milpitas, California, US | 45 | 2000–2021 |
| San Jose, California, US | 31 | 2005–2014 |
| Selanger, MY | 1 | 1999 |
| Chandler, AZ, US | 1 | 1995 |