Inventor
Hisashi Shichijo
Inventor
Plano, TX, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10BElectronic memory devices10%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation10%
G11CStatic stores5%
H03MCoding5%
G06NComputing arrangements based on specific computational models3%
H01CResistors3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
8,134,204'DEMOS transistors with STI and compensated well in drain'20127,915,905'Process and temperature insensitive flicker noise monitor circuit'20117,719,299'Process and temperature insensitive flicker noise monitor circuit'20107,692,217'Matched analog CMOS transistors with extension wells'20107,250,334'Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode'20076,764,892'Device and method of low voltage SCR protection for high voltage failsafe ESD applications'20046,753,202'CMOS photodiode having reduced dark current and improved light sensitivity and responsivity'20046,621,064'CMOS photodiode having reduced dark current and improved light sensitivity and responsivity'20036,576,959'Device and method of low voltage SCR protection for high voltage failsafe ESD applications'20036,512,280'Integrated CMOS structure for gate-controlled buried photodiode'20036,392,263'Integrated structure for reduced leakage and improved fill-factor in CMOS pixel'20026,303,420'Integrated bipolar junction transistor for mixed signal circuits'20015,959,308'Epitaxial layer on a heterointerface'19995,894,145'Multiple substrate bias random access memory device'19995,595,925'Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein'19975,290,719'Method of making complementary heterostructure field effect transistors'19945,238,869'Method of forming an epitaxial layer on a heterointerface'19935,214,298'Complementary heterostructure field effect transistors'19935,164,917'Vertical one-transistor DRAM with enhanced capacitance and process for fabricating'19925,065,132'Programmable resistor and an array of the same'19914,914,053'Heteroepitaxial selective-area growth through insulator windows'19904,910,164'Method of making planarized heterostructures using selective epitaxial growth'19904,713,678'dRAM cell and method'19874,545,034'Contactless tite RAM'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–2012Patents assigned to TEXAS INSTRUMENTS INC (24)· patent assignee history
1985–1999Based in Garland, TX, US· patent location history
1991–2012Based in Plano, TX, US· patent location history
2012Patents assigned to BENAISSA KAMEL (1)· patent assignee history
2012Patents assigned to SHICHIJO HISASHI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 24 | 1985–2012 |
| BENAISSA KAMEL | 1 | 2012 |
| SHICHIJO HISASHIself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 15 | 1991–2012 |
| Garland, Texas, US | 9 | 1985–1999 |