Inventor
Satyendra Sethi
Inventor
Pleasanton, CA, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices41%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10DInorganic electric semiconductor devices9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
G01NInvestigating or analysing materials by determining their chemical or physical properties5%
G02BOptical elements, systems or apparatus5%
G06TImage data processing or generation, in general5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
PatentTitleYear
6,642,529'Methods for the automated testing of reticle feature geometries'20036,433,854'Method of illumination uniformity in photolithographic systems'20026,411,367'Modified optics for imaging of lens limited subresolution features'20026,372,522'Use of optimized film stacks for increasing absorption for laser repair of fuse links'20026,313,542'Method and apparatus for detecting edges under an opaque layer'20016,297,170'Sacrificial multilayer anti-reflective coating for mos gate formation'20016,262,795'Apparatus and method for the improvement of illumination uniformity in photolithographic systems'20016,215,129'Via alignment, etch completion, and critical dimension measurement method and structure'20016,162,650'Via alignment, etch completion, and critical dimension measurement method and structure'20005,952,135'Method for alignment using multiple wavelengths of light'19995,883,011'Method of removing an inorganic antireflective coating from a semiconductor substrate'19995,852,497'Method and apparatus for detecting edges under an opaque layer'19985,776,821'Method for forming a reduced width gate electrode'19985,443,941'Plasma polymer antireflective coating'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Patents assigned to NAT SEMICONDUCTOR CORP (1)· patent assignee history
1995Based in Austin, TX, US· patent location history
1998–2002Patents assigned to VLSI TECHNOLOGY INC (8)· patent assignee history
1998–2003Based in Pleasanton, CA, US· patent location history
1998–2001Based in Pleasonton, CA, US· patent location history
1999Patents assigned to VLSI TECHNOLOGY (1)· patent assignee history
2001Patents assigned to PHILIP SEMICONDUCTORS INC (1)· patent assignee history
2002–2003Patents assigned to KONINKL PHILIPS ELECTRONICS NV (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VLSI TECHNOLOGY INC | 8 | 1998–2002 |
| KONINKL PHILIPS ELECTRONICS NV | 2 | 2002–2003 |
| NAT SEMICONDUCTOR CORP | 1 | 1995 |
| PHILIP SEMICONDUCTORS INC | 1 | 2001 |
| VLSI TECHNOLOGY | 1 | 1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Pleasanton, California, US | 10 | 1998–2003 |
| Pleasonton, California, US | 3 | 1998–2001 |
| Austin, Texas, US | 1 | 1995 |