Inventor
Gerchih Chou
Inventor
San Jose, CA, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores20%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses16%
G06FElectric digital data processing14%
H03KPulse technique10%
H04LTransmission of digital information, e.g. telegraphic communication10%
H04BTransmission7%
H03FAmplifiers6%
H03HImpedance networks, e.g. resonant circuits4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H04QSelecting3%
PatentTitleYear
10,998,020Memory system and memory access interface device thereof202110,998,061Memory system and memory access interface device thereof202110,978,118DDR SDRAM signal calibration device and method202110,916,278Memory controller and memory data receiving method for generate better sampling clock signal202110,741,231Memory access interface device including phase and duty cycle adjusting circuits for memory access signals202010,698,846DDR SDRAM physical layer interface circuit and DDR SDRAM control device202010,643,685Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof202010,630,289On-die-termination circuit and control method for of the same202010,522,204Memory signal phase difference calibration circuit and method201910,382,232Memory controller with adjustable impedance for output terminal201910,347,325DDR4 memory I/O driver201910,056,124Memory control device for repeating data during a preamble signal or a postamble signal and memory control method20189,948,280Two-capacitor-based filter design method and two-capacitor-based filter20189,570,130'Memory system and memory physical layer interface circuit'20179,350,529'Method and apparatus for detecting logical signal'20168,665,921'Method and apparatus of automatic power control for burst mode laser transmitter'20148,648,640'Method and apparatus for clock transmission'20148,410,834'All digital serial link receiver with low jitter clock regeneration and method thereof'20138,363,774'Methods and apparatuses of serial link transceiver without external reference clock'20138,324,982'Integrated front-end passive equalizer and method thereof'20128,115,566'Integrated front-end passive equalizer and method thereof'20128,040,167'Method and apparatus for charge leakage compensation for charge pump'20117,969,202'Fractional-N frequency synthesizer'20117,924,113'Integrated front-end passive equalizer and method thereof'20117,629,854'Switch-capacitor loop filter for phase lock loops'20097,583,117'Delay lock clock synthesizer and method thereof'20097,560,991'Dynamically compensated operational amplifier'20097,498,856'Fractional-N frequency synthesizer'20097,496,161'Adaptive equalization system for a signal receiver'20097,492,197'Charge pump circuit with regulated current output'20097,492,845'Adaptive equalization system for a signal receiver'20097,477,180'Noise shaping comparator based switch capacitor circuit and method thereof'20097,450,041'Error cancelling comparator based switch capacitor circuit and method thereof'20087,405,604'Variable delay clock circuit and method thereof'20087,403,064'Dynamically accelerated operational amplifier and method thereof'20087,388,407'Variable delay clock synthesizer'20087,277,516'Adaptive equalization system for a signal receiver'20077,274,232'Variable delay clock synthesizer'20077,254,194'Automatic gain control for communication receivers'20077,002,931'Power efficient line driver with high performance echo cancellation for 1000BASE-T'20066,614,842'FIR filter architecture for 100Base-TX receiver'20035,790,048'Crosspoint switch with bank-switched memory'19985,734,334'Programmable port for crossbar switch'19985,717,871'Crossbar switch with input/output buffers having multiplexed control inputs'19985,710,550'Apparatus for programmable signal switching'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998Patents assigned to CUBE INC I (4)· patent assignee history
1998–2021Based in San Jose, CA, US· patent location history
2003–2007Patents assigned to INFINEON TECHNOLOGIES CORP (3)· patent assignee history
2007–2021Patents assigned to REALTEK SEMICONDUCTOR CORP (38)· patent assignee history
2012–2014Patents assigned to CHOU GERCHIH (5)· patent assignee history
2012–2014Patents assigned to LIN CHIA-LIANG (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| REALTEK SEMICONDUCTOR CORP | 38 | 2007–2021 |
| CHOU GERCHIHself | 5 | 2012–2014 |
| LIN CHIA-LIANG | 5 | 2012–2014 |
| CUBE INC I | 4 | 1998 |
| INFINEON TECHNOLOGIES CORP | 3 | 2003–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 45 | 1998–2021 |