Inventor
Robert J. Mears
Inventor
Wellesley, MA, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices38%
H10DInorganic electric semiconductor devices36%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
PatentTitleYear
10,937,868Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices202110,937,888Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices202110,879,357Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice202010,879,356Method for making a semiconductor device including enhanced contact structures having a superlattice202010,868,120Method for making a varactor with hyper-abrupt junction region including a superlattice202010,854,717Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance202010,847,618Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance202010,840,337Method for making a FINFET having reduced contact resistance202010,840,336Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods202010,840,388Varactor with hyper-abrupt junction region including a superlattice202010,840,335Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance202010,825,902Varactor with hyper-abrupt junction region including spaced-apart superlattices202010,825,901Semiconductor devices including hyper-abrupt junction region including a superlattice202010,818,755Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance202010,811,498Method for making superlattice structures with reduced defect densities202010,777,451Semiconductor device including enhanced contact structures having a superlattice202010,741,436Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface202010,727,049Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice202010,593,761Method for making a semiconductor device having reduced contact resistance202010,580,866Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance202010,580,867FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance202010,566,191Semiconductor device including superlattice structures with reduced defect densities202010,468,245Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice201910,453,945Semiconductor device including resonant tunneling diode structure having a superlattice201910,361,243Method for making CMOS image sensor including superlattice to enhance infrared light absorption201910,276,625CMOS image sensor including superlattice to enhance infrared light absorption201910,249,745Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice201910,211,251CMOS image sensor including superlattice to enhance infrared light absorption201910,170,604Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers201910,170,560Semiconductor devices with enhanced deterministic doping and related methods201910,170,603Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers201910,109,479Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice201810,084,045Semiconductor device including a superlattice and replacement metal gate structure and related methods20189,972,685Vertical semiconductor devices including superlattice punch through stop layer and related methods20189,941,359Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods20189,899,479'Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods'20189,721,790'Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control'20179,722,046'Semiconductor device including a superlattice and replacement metal gate structure and related methods'20179,716,147'Semiconductor devices with enhanced deterministic doping and related methods'20179,406,753'Semiconductor devices including superlattice depletion layer stack and related methods'20169,275,996'Vertical semiconductor devices including superlattice punch through stop layer and related methods'2016Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2016–2021Patents assigned to ATOMERA INC (39)· patent assignee history
2016Patents assigned to MEARS TECHNOLOGIES INC (1)· patent assignee history
2016–2021Based in Wellesley, MA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ATOMERA INC | 39 | 2016–2021 |
| MEARS TECHNOLOGIES INC | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wellesley, Massachusetts, US | 41 | 2016–2021 |