Inventor
Sheng-Chih Lai
Inventor
Taichung, TW
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices25%
H10DInorganic electric semiconductor devices20%
G11CStatic stores15%
H01LSemiconductor devices13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10NElectric solid-state devices not otherwise provided for8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
PatentTitleYear
10,879,458Memory device202010,644,231Memory device and fabrication method thereof20209,583,350'Memory device and method for fabricating the same'20179,419,010'High aspect ratio etching method'20169,356,040'Junction formation for vertical gate 3D NAND memory'20168,987,700'Thermally confined electrode for programmable resistance memory'20158,975,687'Nonvolatile memory array with continuous charge storage dielectric stack'20158,946,671'Mask read only memory containing diodes and method of manufacturing the same'20158,378,410'Semiconductor device and method of manufacturing the same'20138,343,840'Blocking dielectric engineered charge trapping memory cell with high speed erase'20138,330,210'High-κ capped blocking dielectric bandgap engineered SONOS and MONOS'20128,207,571'Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase'20128,119,481'High-κ capped blocking dielectric bandgap engineered SONOS and MONOS'20127,910,981'Semiconductor device and method of manufacturing the same'20117,880,115'Method for laser annealing to form an epitaxial growth layer'20117,816,727'High-κ capped blocking dielectric bandgap engineered SONOS and MONOS'20107,737,488'Blocking dielectric engineered charge trapping memory cell with high speed erase'20107,247,503'Method of laser annealing to form an epitaxial growth layer'20077,196,924'Method of multi-level cell FeRAM'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2017Patents assigned to MACRONIX INT CO LTD (17)· patent assignee history
2007–2011Based in Hsinchu, TW· patent location history
2010–2015Based in Taichung, TW· patent location history
2012–2015Patents assigned to LAI SHENG-CHIH (8)· patent assignee history
2012–2015Patents assigned to LUE HANG-TING (6)· patent assignee history
2012–2013Patents assigned to LIAO CHIEN-WEI (3)· patent assignee history
2012–2016Based in Elmsford, NY, US· patent location history
2015Patents assigned to LUNG HSIANG-LAN (2)· patent assignee history
2016–2017Based in Zhubei City, TW· patent location history
2020Based in Hsinchu County, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MACRONIX INT CO LTD | 17 | 2007–2017 |
| LAI SHENG-CHIHself | 8 | 2012–2015 |
| LUE HANG-TING | 6 | 2012–2015 |
| LIAO CHIEN-WEI | 3 | 2012–2013 |
| LUNG HSIANG-LAN | 2 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taichung, TW | 8 | 2010–2015 |
| Hsinchu, TW | 4 | 2007–2011 |
| Elmsford, New York, US | 3 | 2012–2016 |
| Hsinchu County, TW | 2 | 2020 |
| Zhubei City, TW | 2 | 2016–2017 |