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Inventor

Vasisht Mantra Vadi

Inventor
San Jose, CA, US

Overview

39→
Patents
2005–2019
Patent span
Physics
Primary field (CPC G)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique40%
G06FElectric digital data processing32%
G06VImage or video recognition or understanding15%
G11CStatic stores7%
H01LSemiconductor devices3%
H10DInorganic electric semiconductor devices3%
H03HImpedance networks, e.g. resonant circuits1%
PatentTitleYear
10,505,541High-voltage tolerant level shifter using thin-oxide transistors and a middle-of-the-line (MOL) capacitor201910,032,763Bulk cross-coupled high density power supply decoupling capacitor20188,543,635'Digital signal processing block with preadder stage'20138,117,577'Determining timing paths within a circuit block of a programmable integrated circuit'20128,001,171'Pipeline FFT architecture for a programmable device'20117,882,165'Digital signal processing element having an arithmetic logic unit'20117,870,182'Digital signal processing circuit having an adder circuit with carry-outs'20117,865,542'Digital signal processing block having a wide multiplexer'20117,860,915'Digital signal processing circuit having a pattern circuit for determining termination conditions'20107,853,632'Architectural floorplan for a digital signal processing circuit'20107,853,636'Digital signal processing circuit having a pattern detector circuit for convergent rounding'20107,853,634'Digital signal processing circuit having a SIMD circuit'20107,849,119'Digital signal processing circuit having a pattern detector circuit'20107,844,653'Digital signal processing circuit having a pre-adder circuit'20107,840,627'Digital signal processing circuit having input register blocks'20107,840,630'Arithmetic logic unit circuit'20107,759,973'Integrated circuit having embedded differential clock tree'20107,518,401'Differential clock tree in an integrated circuit'20097,414,430'Programmable logic device having an embedded differential clock tree'20087,394,708'Adjustable global tap voltage to improve memory cell yield'20087,372,299'Differential clock tree in an integrated circuit'20087,314,174'Method and system for configuring an integrated circuit'20087,286,382'Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability'20077,283,409'Data monitoring for single event upset in a programmable logic device'20077,233,532'Reconfiguration port for dynamic reconfiguration-system monitor interface'20077,233,169'Bidirectional register segmented data busing'20077,218,137'Reconfiguration port for dynamic reconfiguration'20077,196,940'Method and apparatus for a multiplexed address line driver'20077,187,709'High speed configurable transceiver architecture'20077,142,442'Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability'20067,129,765'Differential clock tree in an integrated circuit'20067,129,762'Efficient implementation of a bypassable flip-flop with a clock enable'20067,126,406'Programmable logic device having an embedded differential clock tree'20067,126,372'Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration'20067,109,750'Reconfiguration port for dynamic reconfiguration-controller'20067,109,746'Data monitoring for single event upset in a programmable logic device'20067,071,756'Clock multiplexing system'20066,975,145'Glitchless dynamic multiplexer with synchronous and asynchronous controls'20056,911,842'Low jitter clock for a physical media access sublayer on a field programmable gate array'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2013Patents assigned to XILINX INC (37)· patent assignee history
2005–2007Based in Mountain View, CA, US· patent location history
2006–2013Based in San Jose, CA, US· patent location history
2012–2013Patents assigned to CHING ALVIN Y (2)· patent assignee history
2012–2013Patents assigned to VADI VASISHT M (2)· patent assignee history
2012Patents assigned to FREEMAN RICHARD D (1)· patent assignee history
2018–2019Patents assigned to QUALCOMM INC (2)· patent assignee history
2018–2019Based in San Diego, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
XILINX INC372005–2013
CHING ALVIN Y22012–2013
QUALCOMM INC22018–2019
VADI VASISHT Mself22012–2013
FREEMAN RICHARD D12012
Locations
LocationPatentsSpan
San Jose, California, US342006–2013
Mountain View, California, US32005–2007
San Diego, California, US22018–2019