Inventor
Jason Janesky
Inventor
Gilbert, AZ, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores27%
H10NElectric solid-state devices not otherwise provided for23%
H10BElectronic memory devices15%
H01LSemiconductor devices13%
B82YSpecific uses or applications of nanostructures8%
H01FMagnets7%
G01RMeasuring electric variables2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
H01JElectric discharge tubes or discharge lamps1%
PatentTitleYear
11,088,317Structures and methods for shielding magnetically sensitive components202110,923,170Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines202110,897,008Magnetoresistive stacks with an unpinned, fixed synthetic anti-ferromagnetic structure and methods of manufacturing thereof202110,707,410Magnetoresistive stacks with an unpinned, fixed synthetic anti-ferromagnetic structure and methods of manufacturing thereof202010,608,172Magnetoresistive structure having two dielectric layers, and method of manufacturing same202010,600,460Perpendicular magnetic memory using spin-orbit torque202010,262,713Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines201910,230,046Magnetoresistive structure having two dielectric layers, and method of manufacturing same201910,199,571Methods of manufacturing magnetoresistive MTJ stacks having an unpinned, fixed synthetic anti-ferromagnetic structure20199,954,163Structures and methods for shielding magnetically sensitive components20189,893,275'Magnetoresistive structure having two dielectric layers, and method of manufacturing same'20189,793,468'Magnetoresistive MTJ stack having an unpinned, fixed synthetic anti-ferromagnetic structure'20179,595,665'Non-reactive photoresist removal and spacer layer optimization in a magnetoresistive device'20179,548,442'Magnetoresistive structure having two dielectric layers, and method of manufacturing same'20179,543,041'Configuration and testing for magnetoresistive memory to ensure long term continuous operation'20179,455,015'High temperature data retention in magnetoresistive random access memory'20169,444,037'Magnetoresistive memory element having a metal oxide tunnel barrier'20169,391,264'MRAM having an unpinned, fixed synthetic anti-ferromagnetic structure'20169,293,698'Magnetoresistive structure having a metal oxide tunnel barrier and method of manufacturing same'20169,281,168'Reducing switching variation in magnetoresistive devices'20169,136,464'Apparatus and process for manufacturing ST-MRAM having a metal oxide tunnel barrier'20159,093,637'MRAM synthetic anitferomagnet structure'20159,093,640'Method for manufacturing and magnetic devices having double tunnel barriers'20158,754,460'MRAM synthetic anitferomagnet structure'20148,685,756'Method for manufacturing and magnetic devices having double tunnel barriers'20148,497,538'MRAM synthetic antiferromagnet structure'20137,572,645'Magnetic tunnel junction structure and method'20097,329,935'Low power magnetoresistive random access memory elements'20087,235,408'Synthetic antiferromagnetic structure for magnetoelectronic devices'20077,184,300'Magneto resistance random access memory element'20077,158,407'Triple pulse method for MRAM toggle bit characterization'20077,129,098'Reduced power magnetoresistive random access memory elements'20066,967,366'Magnetoresistive random access memory with reduced switching field variation'20056,898,112'Synthetic antiferromagnetic structure for magnetoelectronic devices'20056,818,961'Oblique deposition to induce magnetic anisotropy for MRAM cells'20046,720,597'Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers'20046,654,278'Magnetoresistance random access memory'20036,633,498'Magnetoresistive random access memory with reduced switching field'20036,579,625'Magnetoelectronics element having a magnetic layer formed of multiple sub-element layers'20036,545,906'Method of writing to scalable magnetoresistance random access memory element'20036,531,723'Magnetoresistance random access memory for improved scalability'20036,515,341'Magnetoelectronics element having a stressed over-layer configured for alteration of the switching energy barrier'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2004Patents assigned to MOTOROLA INC (7)· patent assignee history
2003–2021Based in Gilbert, AZ, US· patent location history
2003–2005Based in Mesa, AZ, US· patent location history
2004–2008Patents assigned to FREESCALE SEMICONDUCTOR INC (8)· patent assignee history
2009–2021Patents assigned to EVERSPIN TECHNOLOGIES INC (27)· patent assignee history
2013Patents assigned to AKERMAN BENGT J (1)· patent assignee history
2014Patents assigned to AGGARWAL SANJEEV (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| EVERSPIN TECHNOLOGIES INC | 27 | 2009–2021 |
| FREESCALE SEMICONDUCTOR INC | 8 | 2004–2008 |
| MOTOROLA INC | 7 | 2003–2004 |
| AGGARWAL SANJEEV | 1 | 2014 |
| AKERMAN BENGT J | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Gilbert, AZ, US | 34 | 2003–2021 |
| Mesa, AZ, US | 8 | 2003–2005 |