Inventor
Jindrich Zejda
Inventor
Saratoga, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
G06NComputing arrangements based on specific computational models37%
G11CStatic stores3%
PatentTitleYear
11,061,654Synchronization of concurrent computation engines202111,036,827Software-defined buffer/transposer for general matrix multiplication in a programmable IC202111,016,775Neural network operation reordering for parallel execution202111,003,429Compile-time scheduling202110,943,039Software-driven design optimization for fixed-point multiply-accumulate circuitry202110,922,146Synchronization of concurrent computation engines202110,846,621Fast context switching for computational networks202010,846,201Performance debug for networks202010,761,822Synchronization of computation engines with non-blocking instructions202010,678,509Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators202010,572,409Sparse matrix processing circuitry202010,515,135Data format suitable for fast massively parallel general matrix multiplication in a programmable IC201910,354,733Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC20199,842,187'Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design'20178,321,824'Multiple-power-domain static timing analysis'20128,091,049'Integrated single spice deck sensitization for gate level tools'20127,861,198'Distorted waveform propagation and crosstalk delay analysis using multiple cell models'20107,263,676'Method and apparatus for detecting and analyzing the propagation of noise through an integrated circuit'20077,007,252'Method and apparatus for characterizing the propagation of noise through a cell in an integrated circuit'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2012Patents assigned to SYNOPSYS INC (5)· patent assignee history
2006–2012Based in Sunnyvale, CA, US· patent location history
2012Patents assigned to ZEJDA JINDRICH (2)· patent assignee history
2012Patents assigned to DING LI (1)· patent assignee history
2017–2021Patents assigned to XILINX INC (7)· patent assignee history
2017–2021Based in Saratoga, CA, US· patent location history
2020–2021Patents assigned to AMAZON TECH INC (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AMAZON TECH INC | 7 | 2020–2021 |
| XILINX INC | 7 | 2017–2021 |
| SYNOPSYS INC | 5 | 2006–2012 |
| ZEJDA JINDRICHself | 2 | 2012 |
| DING LI | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 14 | 2017–2021 |
| Sunnyvale, California, US | 5 | 2006–2012 |